153 results on '"Liao, Huailin"'
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2. An All-Digital Outphasing Transmitter IC for Ka-Band Bit-to-RF Concurrent Multi-Beam DBF Array
3. A Single-Ended Digital Transmitter Based on I/Q-Sharing Switched-Capacitor Power Amplifier and Third-Order Harmonic-Rejection
4. A 2.85-mm2 Wideband RF Transceiver in 40-nm CMOS for IoT Micro-Hub Applications
5. A 24 GHz Self-Calibrated All-Digital FMCW Synthesizer With 0.01% RMS Frequency Error Under 3.2 GHz Chirp Bandwidth and 320 MHz/µs Chirp Slope
6. A 2.85mm2 RF Transceiver in 40nm CMOS for IoT Micro-Hub Applications
7. A 65 mW fully integrated UHF-band CMMB tuner in 65 nm CMOS process
8. A Gm-Compensated 46-101 GHz Broadband Power Amplifier for High-Resolution FMCW Radars
9. A Hybrid Digital Transmitter Architecture for High- Efficiency and High-Speed Applications
10. A physics-based equivalent-circuit model for on-chip symmetric transformers with accurate substrate modeling
11. 32.5 A 24GHz Self-Calibrated ADPLL-Based FMCW Synthesizer with 0.01% rms Frequency Error Under 3.2GHz Chirp Bandwidth and 320MHz/μs Slope
12. A 12-Bit 0.5–2.4-GHz 0.65°-Peak-INL Parasitic-Insensitive Digital-to-Phase Converter
13. A 12-GHz Calibration-Free All-Digital PLL for FMCW Signal Generation With 78 MHz/μs Chirp Slope and High Chirp Linearity
14. A 0.5-V 3.69-nW Complementary Source-Follower-C Based Low-Pass Filter for Wearable Biomedical Applications
15. Monte Carlo simulations of gas flow and heat transfer in vacuum packaged MEMS devices
16. High-performance integrated inductor and effective crosstalk isolation using post-CMOS selective grown porous silicon (SGPS) technique for RFIC applications
17. Temperature Effects on the Performance of On-Chip Spiral Inductors Used in RF(MM)ICs
18. An 81–99 GHz Tripler with Fundamental Cancellation and 3rd Harmonic Enhancement Technique in 40-nm CMOS
19. A 12-GHz All-Digital Calibration-Free FMCW Signal Generator Based on a Retiming Fractional Frequency Divider
20. A Reverse-RSSI Logarithmic Power Detector With +35-dBm Maximum Detectable Power in 180-nm CMOS
21. A 0.5-V Ultra-Low-Power Low-Pass Filter with a Bulk-Feedback Technique
22. A 28 GHz 8-Bit Calibration-Free LO-Path Phase Shifter using Transformer-Based Vector Summing Topology in 40 nm CMOS
23. A Calibration-Free Fractional-N ADPLL using Retiming Architecture and a 9-bit 0.3ps-INL Phase Interpolator
24. A 2.9 GHz Variable Inductor-Based DCO With 1.3 kHz Frequency Resolution for FMCW Radar Applications
25. A Low Power 0.4-1 Ghz Receiver Front-End with an Enhanced Third-Order-Harmonic-Rejecting Series N-Path Filter
26. A Low Power Analog Baseband for IoT Applications in 40 nm CMOS
27. The enhancement of Q factor for patterned ground shield inductors at high temperatures
28. On-Chip Self-Interference Canceller with Variable Inductor Based Electrical Balance Network for Full Duplex Systems
29. 2.4-GHz Pre-bias RF Energy Harvesting Rectifier with -35-dBm Sensitivity for Self-powered Chips
30. A low power and low in-band phase noise W-band frequency synthesizer in 65 nm CMOS
31. A 2.4-mW interference-resilient receiver front end with series N-path filter-based balun for body channel communication
32. A 43.2 μW 2.4 GHz 64-QAM Pseudo-Backscatter Modulator Based on Integrated Directional Coupler
33. A Digital Phase Noise Cancelling Scheme for Ring Oscillator-based Fractional-N ADPLL
34. Quadrature amplitude modulated backscatter for 2.4GHz self-powered chips
35. A novel SCR ESD protection structure for RF power amplifier
36. A 12-bit 2.5 GHz 0.37ps-Peak-INL Digital-to-Time Converter with Parasitic-Insensitive Charge-Based Phase Interpolator
37. A Low Power SAW-less 2.4-GHz Receiver with an LC Matched Series N-path Filter
38. A low power triple-mode parallel-processing CMOS receiver for BD-II/GPS/Galileo joint navigation applications
39. A CMOS-compatible silicon substrate optimization technique and its application in radio frequency crosstalk isolation
40. An 89 μW MICS/ISM band receiver for ultra-low-power applications
41. A tunable transformer-based CMOS directional coupler for UHF RFID readers
42. A single-poly EEPROM with low leakage charge pump and peripheral circuits for passive RFID tag in a standard CMOS technology
43. Design of a 3–5-GHz ultrawideband BiFET mixer using 0.35-μm SiGE BiCMOS technology
44. A low-power calibration-free fractional-N digital PLL with high linear phase interpolator
45. A 7.9 fJ/conversion-step 10-bit 125 MS/s SAR ADC with simplified power-efficient digital control logic
46. Characterization of symmetrical spiral inductor in 0.35 μm CMOS technology for RF application
47. The behavior of yttrium implants in H13 steel under high temperature oxidation
48. A 51-nW 32.7-kHz CMOS relaxation oscillator with half-period pre-charge compensation scheme for ultra-low power systems
49. A 93.7% peak efficiency DC-DC buck converter with all-pass network based passive level shifter in 55 nm CMOS
50. CMOS integrated low TX noise digital transmitter with tunable directional coupler for high performance UHF RFID reader
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