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A fully integrated 79 to 87 GHz frequency synthesizer is proposed, which combines a W-band push–push ×4 frequency multiplier and a K-band divider-less phase locked loop (PLL) with sampling phase detector. The circuit is verified in a standard 65 nm CMOS process. The frequency synthesizer consumes 54 mW totally, and the measured phase noise of divide-by-2 frequency is −100.1 and −106.2 dBc/Hz at 100 kHz and 1 MHz offset, respectively. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2014–2018, 2014

This article presents a low power triple-mode parallel-processing CMOS receiver for BD-II/GPS/Galileo joint navigation applications. An innovative image rejecting parallel-processing architecture is proposed, which utilizes a single frequency synthesizer, shares the front-end, and adopts two complex band-pass filters in two channels separately, aiming for the receiving of BD-II B1/GPS L1/GALILEO L1 multistandard navigation signals simultaneously. The proposed triple-mode parallel-processing receiver is fabricated in a 0.18 μm CMOS process with 22.2 mA power consumption under the triple-mode parallel-processing navigation. Measured results show that it has a maximum conversion gain of 101.5 dB and a double-side-band noise figure of 3.3 dB with the fixed IF of 7*f0 (f0 = 1.023 MHz), tunable IF bandwidth of 2*f0/4*f0, and more than 34 dB image rejection. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2616–2620, 2013

In this paper, a complementary metal-oxide semiconductor (CMOS)-compatible silicon substrate optimization technique is proposed to achieve effective isolation. The selective growth of porous silicon is used to effectively suppress the substrate crosstalk. The isolation structures are fabricated in standard CMOS process and then this post-CMOS substrate optimization technique is carried out to greatly improve the performances of crosstalk isolation. Three-dimensional electro-magnetic simulation is implemented to verify the obvious effect of our substrate optimization technique. The morphologies and growth condition of porous silicon fabricated have been investigated in detail. Furthermore, a thick selectively grown porous silicon (SGPS) trench for crosstalk isolation has been formed and about 20dB improvement in substrate isolation is achieved. These results demonstrate that our post-CMOS SGPS technique is very promising for RF IC applications.

A fully integrated ultrawideband (UWB) bipolar cascode with metal oxide semiconductor field effect transistor (BiFET) mixer using standard commercial 0.35-μm silicon germanium bipolar complementary metal oxide semiconductor technology was first proposed and fabricated in this study. This presented BiFET mixer using bipolar junction transistor as the transconductor stage and metal oxide semiconductor field effect transistor as the switch stage to achieve noise power and linearity trade-off. This 3–5-GHz UWB mixer achieves a conversion gain of 4.5 ± 0.5 dB at the designed band. The mixer core draws a current of 2.5 mA from a supply voltage of 3 V, while consumes chip area of 0.9 × 0.9 mm2. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 965–968, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22305

Characteristics of symmetrical spiral inductor in differential mode is studied and optimized in this work. The characteristics of interest include inductor value, quality factor, peak frequency and self-resonance frequency. Both single-layer and double-layer inductor using top metals are characterized. Inductor excited in differential mode and single-ended mode are characterized for comparison. The optimized symmetrical spiral inductors are fabricated in standard digital 0.35 μm CMOS process. Experimental results show 60–100% improvement of quality factor and peak frequency, meanwhile 10–20% improvement of self-resonance frequency by exciting the symmetrical spiral inductors in differential mode compared with single-ended mode. To further validate the characterized inductor, the differential spiral inductors are adopted in optimizing low power and low phase noise fully integrated 2.4 GHz voltage-controlled oscillator (VCO). The designed VCO achieved phase noise of more than −105 dBc/Hz at 100 kHz offset with approximately 4.5 mA at 3.0 V supply.

The penetration depth of yttrium ions extracted at 30 kV from a metal vapor vacuum arc (MEVVA) source reaches approximately 50 nm in H13 steel. For a pre-set dose of 3×10 17 cm −2 , the retained dose decreases (1.04×10 17 –6.2×10 16 cm −2 ) with increasing beam flux (25–76 μA cm −2 ). During high temperature (600–800°C) oxidation, yttrium implants have no change in quantity, but migrate inwards and redistribute themselves. As the dose is increased (up to 1×10 18 cm −2 ) in-going yttrium is redistributed almost uniformly within the oxidation scale; when the beam flux is increased the peak of yttrium profile shifts to a much deeper position (245 nm for 76 μA cm −2 ). Yttrium redistribution is not sensitive to oxidation time. A tentative explanation is presented.