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This article reports Si-passivated Ge nFinFETs with significantly improved GmSAT/SSSAT and positive bias temperature instability (PBTI) reliability enabled by an improved replacement metal gate (RMG) high- ${k}$ last process. SiO2 dummy gate oxide (DGO) deposition on Ge fin is shown to form (Si x )Ge1- x O y , which is, compared to a pure SiO2, more difficult to remove completely during the dry clean prior to the gate-stack formation. By extending the DGO removal clean, improved PBTI reliability, reduced ${D}_{{\text {IT}}}$ , and increased electron mobility are demonstrated. Moreover, by suppressing the Ge channel oxidation through the choice of less-oxidizing DGO or inserting an Si-cap layer prior to the DGO deposition, a greatly improved long-channel electron mobility is obtained at a scaled fin width. Finally, together with the PBTI maximum ${V}_{{\text {OV}}}$ of 0.13 V, the best GmSAT/SSSAT of 5.4 is achieved, which is today’s record value among the sub-100-nm- ${L}_{g}$ n-channel Ge Fin and gate-all-around nanowire FETs. These results clearly show the importance of the pre-gate-stack channel surface preparation on the scaled Ge FinFETs to benefit from a previously optimized Si-passivated Ge gate-stack.

The implementation of a barrier potential layer underneath the channel region, well known as Ground Plane (GP) implantation, and its influence on the performance of relaxed germanium pFinFET devices is investigated in this manuscript. This study aims to explain the fin width dependence of the threshold voltage from experimental data and evaluates the ground plane doping concentration and its depth influence on relaxed p-type channel germanium FinFET parameters, as threshold voltage, transconductance and subthreshold swing, through Technology Computer-Aided Design (TCAD) numerical simulations. The threshold voltage variation reaches up to 80 mV from the narrowest device to the widest one, considering the studied range of ground plane doping concentration. Concerning the subthreshold swing parameter, neither the GP doping concentration, nor its depth play a significant role since the electrostatic coupling is predominant.

Nano-ridge engineering (NRE) is a novel method to monolithically integrate III–V devices on a 300 mm Si platform. In this work, NRE is applied to InGaP/GaAs heterojunction bipolar transistors (HBTs), enabling hybrid III-V/CMOS technology for RF applications. The NRE HBT stacks were grown by metal-organic vapor-phase epitaxy on 300 mm Si (001) wafers with a double trench-patterned oxide template, in an industrial deposition chamber. Aspect ratio trapping in the narrow bottom part of a trench results in a threading dislocation density below 106∙cm−2 in the device layers in the wide upper part of that trench. NRE is used to create larger area NRs with a flat (001) surface, suitable for HBT device fabrication. Transmission electron microscopy inspection of the HBT stacks revealed restricted twin formation after the InGaP emitter layer contacts the oxide sidewall. Several structures, with varying InGaP growth conditions, were made, to further study this phenomenon. HBT devices—consisting of several nano-ridges in parallel—were processed for DC and RF characterization. A maximum DC gain of 112 was obtained and a cut-off frequency ft of ~17 GHz was achieved. These results show the potential of NRE III–V devices for hybrid III–V/CMOS technology for emerging RF applications.

This paper describes our recent research progress on high-mobility Ge-channel n/pFETs. Gate stack, junction and contact are the key challenging components of Ge n/pFETs. Through the improvement of those unit modules, the electrical performance and reliability of Ge FinFET and gate-all-around (GAA) nanowire (NW) pFETs have been improved. Remaining technical challenges for the realization of high performance and reliable Ge n/pFETs will be discussed.

In this work, we will address the opportunities of a hybrid III-V/CMOS technology for next generation wireless communication, beyond 5G, moving to operating frequencies above 100GHz. Challenges related to III-V upscaling and CMOS co-integration using 3D technologies will be discussed.

This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated on 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow, excellent electrical performance is demonstrated: the $Q$ factor is increased to 25 as compared to our previous work, $I_{ \mathrm{\scriptscriptstyle ON}} = \textsf {500}~\mu \text{A}/ \mu \text{m}$ at $I_{ \mathrm{\scriptscriptstyle OFF}} = \textsf {100}$ nA/ $\mu \text{m}$ is achieved, approaching the best published results on Ge finFETs. Good negative-bias temperature instability reliability is also maintained, thanks to the use of Si-cap passivation. The process flow developed for the fabrication of the single Ge nanowire (NW) is adapted and vertically stacked strained Ge NWs featuring 8-nm channel diameter are successfully demonstrated. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs after the most challenging steps of the process integration flow: 1.7-GPa uniaxial-stress is demonstrated along the Ge wire, which originates from the lattice mismatch between the Ge source/drain and the Si0.3Ge0.7 SRB.

3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for nMOS and pMOS fabrication, respectively. Device matching, analog, and RF performance of the top tier devices are in-line with the state-of-the-art Si technology processed at high temperature (>1000 °C). JL devices operate at reduced electric field and can meet in specification reliability (10-year reliable operation at ${V}_{\textsf {G}}= {V}_{\textsf {th}}+ 0.6$ V, 125 °C), even without the use of “reliability” anneal. The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding. Comparison with silicon-on-insulator devices fabricated with the same low-temperature flow shows no impact on device electrical performance from the Si layer transfer.

In this letter, evidence of plasma-induced damage (PID) occurring in ${p}$ -type FinFET Germanium devices due to BEOL processing is reported. The ability of high-pressure anneal (HPA) (20 min at 450° with 20 atm pressure) to cure this damage is investigated by comparing different ambients (hydrogen and deuterium) with the reference case without HPA. The degradation and partial recovery during anneal of the threshold voltage, the transconductance, and the subthreshold slope are observed. Further, bias temperature instability stress is employed to evaluate the impact of PID in terms of reliability. It is found that the damage observed in the dc and reliability measurements is more efficiently cured by the H2 ambient than the D2 ambient.

Epitaxial growth of strained and defect free SiGe layers grown with disilane and digermane was investigated. This precursors set allows to cover a broad range of Ge concentration (15–65%) at low temperatures (400–550 °C). It was shown that change of carrier gas (from H2 to N2) does not increase SiGe growth rate but significantly reduces Ge concentration. Increase of total process pressure considerably reduces SiGe growth rate which is attributed to peculiarities of digermane decomposition and influence of hydrogen surface passivation on disilane decomposition. It was shown that both disilane and digermane can be successfully combined with conventional precursors like silane and germane. These experiments suggested that digermane decomposition is the main driver of the growth rate increase during SiGe growth. Based on the presented data we demonstrated growth of different SiGe/Si and SiGe/Ge stacks with high quality necessary for production of gate all around field effect transistors.

Strained Ge p-channel gate-all-around (GAA) devices with Si-passivation are demonstrated on high-density 45-nm active pitch starting from 300-mm SiGe strain relaxed buffer wafers. While single horizontal Ge nanowire (NW) devices are demonstrated, the process flow described in this paper can be adjusted to make vertically stacked horizontal Ge NWs to increase the drive per footprint. The demonstrated short-channel devices have round Ge NWs with 9-nm diameter and are the Ge GAA devices with the smallest channel and gate dimensions ( $L_{G}= 40$ nm) published to date. Electrostatics and off-state leakage are maintained down to the shortest gate lengths studied, showing drain-induced barrier lowering of 30 mV/V and sub-20 nA/ $\mu \text{m}~I_{\mathrm{\scriptscriptstyle off}}$ at $V_{\mathrm {{\text {DD}}}}= -0.5$ V and $L_{G}= 40$ nm. The short-channel device subthreshold slope SS and performance can be further improved by use of high-pressure annealing in hydrogen, yielding the best SSLIN and SSSAT of 71 and 76 mV/dec reported so far for any $L_{G}= 40$ -nm Ge pMOS channel device.

High mobility channel materials like SiGe, Ge and IIIV receive lots of interest in order to enable the continuation of Moore’s path during the upcoming technology nodes. Recently Si-cap-free SiGe passivation with the number of interface states (NIT) down to 2 1011 cm-2 have been demonstrated. [1-3] A clear correlation was established between Ge-content in the SiGe-oxide and NIT. Unfortunately no process information has been provided on how the Ge-oxide-free interlayers were obtained. In a separate study the impact of HF, HCl and SC1 cleaning solution on the SiGe surface and oxide composition was reported. [4] A comparison of SiGe Gate-All-Around (GAA) and FinFET devices using a Si-cap-free SiGe 25% passivation scheme in a replacement metal gate (RMG) integration indicate the device performance is improved by a TMAH (aq) treatment prior to SiGe interlayer formation and high-k deposition. [5] Here the formation of a SiGe wet chemical oxide will be presented. The impact of dummy gate processing on the interlayer composition is reported. Also the impact of a TMAH (aq) treatment prior to chemical oxide formation has been analyzed and will be reported. Blanket strained SiGe 25% and 45% were grown by epitaxy. The SiGe-substrate and -oxide composition were measured by angle-resolved XPS using the Si2p and Ge3d peaks. The Ge3d peak is fitted with three different compounds: elemental Ge, GeO2 and Ge-suboxide. The angle dependence lets us estimate the distribution of the different components with respect to the sample top surface. An concentration increase with increasing angle (relative to the surface normal) indicates the compound is located closer to the sample surface. And reversely a concentration increase with increasing angle indicates the compound is located deeper into the sample. A native oxide was grown on SiGe 25 and 45% by exposing the wafers to the cleanroom air for approx. 1 week. The native oxide was found to be stoichiometric or nearly stoichiometric with a uniform Ge content throughout the oxide for SiGe 25 and 45% respectively. A wet chemical oxide was grown using an ‘imec clean’ [6] having a final O3/HCl (aq) rinse. The wet chemical oxide is Ge-poor compared to the SiGe substrate. No or only a small variation in Ge content of the SiGe-oxide is seen with ARXPS. However the fraction Ge-suboxide decreases with increasing angle, indicating the Ge-suboxide are located deeper within the sample, so closer to the SiGe-oxide/SiGe-substrate interface. The Ge-content of the SiGe-substrate after wet chemical oxidation shows a weak incident-angle-dependence, indicative a limited Ge enrichment of the SiGe substrate towards the SiGe-oxide/-substrate interface. The low Ge content of the SiGe-oxide is attributed to the water solubility of GeO2. The increase in Ge-content towards the SiGe-oxide/-substrate can be (at least partially) attributed to the poor water solubility of Ge-suboxide. The small increase in Ge content of the SiGe substrate can be attributed to the thermodynamically preferred oxidation of Si over Ge. The combined impact of dummy gate deposition, spike anneal and dummy gate removal prior to SiGe interlayer formation was investigated by AR-XPS and SIMS. The temperature used during spike anneal was found to have a significant impact on the Ge-content of the SiGe-oxide formed during an O3-last imec clean. The results will be reported in detail at the conference. The impact of TMAH (aq) on the chemical oxide composition and surface roughness will also be reported. TMAH (aq) was found to improve SiGe device performance. [5] Also the interaction with the subsequent HfO2 deposition will be reported. In summary SiGe is found to behave as a non-linear combination of Si and Ge. In HF-free aqueous solutions, the SiGe oxide composition is a combination of (1) thermodynamically preferred oxidation of Si versus Ge; (2) poor water-solubility of SiO2 and/or its low solubilization rate; and (3) fast dissolution of GeO2 but slow dissolution of Ge-suboxides. [1] CH Lee et al. VLSI 2016. [2] S. Siddiqui et al. presented MRS Spring Meeting 2016. [3] CH Lee et al. IEDM 2016. [4] S.L. Heslop et al. ECS Trans 69 (2015) 287. [5] H. Mertens et al VLSI 2015. [6] M. Meuris et al. Solid State Phenom, July 1995, p. 109. Figure 1

SiGe quantum-well pMOSFETs have recently been introduced for enhanced performance of transistors. Quite surprisingly, a significant reduction in negative bias temperature instability (NBTI) was also found in these devices. Furthermore, a stronger oxide field acceleration of the degradation in SiGe devices compared with Si devices was reported. These observations were speculated to be a consequence of the energetical realignment of the SiGe channel with respect to the dielectric stack. As these observations were made on large-area devices, only the average contribution of many defects to NBTI could be studied. In order to reveal the microscopic reasons responsible for the improved reliability, a detailed study of single defects is performed in nanoscale devices. To provide a detailed picture of single charge trapping, the step-height distributions for different device variants are measured and found to follow a unimodal and bimodal distribution. This finding suggests two conducting channels, one in the SiGe and one in the thin Si cap layer. We, furthermore, demonstrate that similar trap depth distributions are present among the device variants supported by a similar stress bias dependence of the capture times of the identified single defects. We conclude that NBTI is primarily determined by the dielectric stack and not by the device technology.

The susceptibility of conventional silicon p-channel MOS transistors to negative bias temperature instabilities (NBTIs) is a serious threat to further device scaling. One possible solution to this problem is the use of a SiGe quantum-well channel. The introduction of a SiGe layer, which is separated from the insulator by a thin Si cap layer, not only results in high mobilities but also superior reliability with respect to NBTI. In part one of this paper, we provide experimental evidence for reduced NBTI by thoroughly studying single traps in nanoscale devices. In this paper, we present detailed TCAD simulations and employ the four-state nonradiative multiphonon model to determine the energetical and spatial positions of the identified single traps. The found trap levels agree with the defect bands estimated in large-area devices. Our conclusions are also supported by the observation of similar activation energies for defects present in transistors of various device geometries. From the calibrated TCAD simulations data, an impressive boost of the time-to-failure for the SiGe transistor can be predicted and explained.

Electron beam (EB) metrology of Ge channel gate-all-around (GAA) FET (field effect transistor) was investigated. Ge-GAA FET is one of the promising candidates for high performance pMOS device of future node. Ge is superior to Si in hole mobility which can be enhanced further by applying compressive channel strain in GAA structure with SiGe strain relaxed buffer (SRB). Coincide with this advantage, channel buckling could happen more easily. Thus, a monitoring method of channel buckling is required. Chemical instability of Ge is another issue in fabrication process. It is suspected that EB irradiation during SEM inspection could cause the deterioration of device performance. On this background, following two evaluations were performed. The first one is quantitative evaluation of channel buckling. It is found that the channel buckling can be quantified with a proposed buckling index. The second one is assessment of the EB-induced damage on the electrical properties. The results showed that EB irradiation on Ge channels does not affect the device performance when the device is annealed adequately. In conclusion, EB metrology is effective for the evaluation of channel buckling and applicable to Ge channels without deterioration of the device performance.

In this paper, we demonstrate GaAs/InGaP HBTs grown on a 300 mm Si substrate. A DC current gain of ~112 and breakdown voltage, BV CBO , of 10 V is achieved. The emitter-base and base-collector diodes show an ideality factor of ~1.2 and ~1.4, respectively. This demonstration shows the potential for enabling a hybrid III-V CMOS/ technology for 5G and mm-wave applications, not limited to GaAs but which can also be extended to InGaAs on a 300 mm Si substrate.

We have demonstrated Ge nFinFETs with a record high $\text{G}_{\text{mSA}\Gamma}/\text{SS}_{\text{SAT}}$ and PBTI reliability by improving the RMG high-k last process. The SiO 2 dummy gate oxide (DGO) deposition and removal processes have been identified as knobs to improve electron mobility and PBTI reliability even with a nominally identical Si-passivated Ge gate stack. Surface oxidation of Ge channel during the DGO deposition is considered to impact the final gate stack. By suppressing the Ge channel surface oxidation, increasing mobility with decreasing fin width is obtained, whereas PBTI reliability, $\text{D}_{\text{IT}}$ of scaled fin as well as high-field mobility are improved by extending the DGO in-situ clean process, resulting in the record $\text{Gm}_{\text{SAT}}/\text{SS}_{\text{SAT}}$ of 5.4 at 73 nm Lg.

This paper demonstrates high performance strained p-type double stacked Ge Gate-AlI-Around (GAA) devices at significantly reduced gate lengths $(\text{L}_{\text{G}}\sim 25\text{nm})$ compared to our previous work. Excellent electrostatic control is maintained down to $\text{L}_{\text{G}}=25$ nm by using extension-less scheme, while the performance is kept by appropriate spacer scaling and implementation of highly B-doped Ge or GeSn as source/drain (S/D) material.

3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic V th tuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer transfer, providing a close proximity to the top tier device, as well as a uniform and high quality thermal back oxide. A threshold voltage tuning of ~103mV/V and ~139mV/V is obtained in p-and nMOS top tier junction-less devices, respectively, over a back gate bias range of +/-2V. BTI reliability measurements show no detrimental impact of the back gate bias. Back-gating can therefore be used to enhance the $I_{ON}$ performance with no reliability penalty. The buried metal line is also shown to lower crosstalk by metal shielding insertion between top and bottom tier metal lines, with a reduction larger than 10dB up to 45GHz.

We have measured the low-frequency 1/ ${f}$ noise of Si0.55Ge0.45 ${p}$ MOSFETs with a Si capping layer and SiO2/HfO2/TiN gate stack as a function of frequency, gate voltage, and temperature (100–440 K). The magnitude of the excess drain voltage noise power spectral density ( $\textit{S}_{ {vd}}$ ) is unaffected by negative-bias-temperature stress (NBTS) for temperatures below ~250 K, but increases significantly at higher temperatures. The noise is described well by the Dutta-Horn model before and after NBTS. The noise at higher measuring temperatures is attributed primarily to oxygen-vacancy and hydrogen-related defects in the SiO2 and HfO2 layers. At lower measuring temperatures, the noise also appears to be affected strongly by hydrogen-dopant interactions in the SiGe layer of the device.

The lower effective mass of germanium compared to silicon makes its quite attractive for future high-performance applications, since high hole mobility material is required for p-type channel devices [1]. In combination with FinFET structures, which present a strong electrostatic coupling [2], it give rises to a promising future device, Ge pFinFET. This work analyses the influence of low temperature effects on static parameters such as threshold voltage (VT), transcondunctance (gm) and subthreshold swing (SS) of strained and relaxed Ge pFinFET devices. The gate stack layer is composed of a paritally oxidized Si passivation layer, hafnium oxide (HfO2) and TiN. The temperature impact is analyzed from 200 K down to 77 K. The devices used in this work have been fabricated on a p-type silicon substrate at Imec/Belgium. There are two diffent STI last processes under evaluation. The first one is the strained channel, whereby a thin Ge layer has been grown on top of a thicker layer of SiGe relaxed buffer (SRB) on a silicon wafer. The other is a relaxed channel, where a thicker Ge layer has been grown on top of the silicon substrate. The planar device dimensions are fin width (Wfin) of 20 nm and geometric channel length (LG) of 1 µm and 4 fins in parallel. All measurements were carried out in linear operation. As the temperature is varied from 200 K down to 77 K one clearly observes that the drain current (IDS) is increased and the curves shift to more negative values, as shown in Fig. 1. The temperature reduction causes the Ge intrinsic concentration to drop, which in turns results in a lower Fermi level value and consequently a threshold voltage (VT) value shift towards positive values [3]. On the other hand, as presented in Fig. 2 the temperature effect is not strong for both relaxed and strained devices, since the VT over temperature ratio values are quite low and similar, 3.25x10-4 V/K and 3.7x10-4 V/K, respectively. The IDS improvement is associated to the carrier mobility increase with the low temperature [4]. Furthermore, the difference between the IDS levels (ΔIDS) for a strained device and relaxed one (Fig. 1) is due to the impact of the strain that boosts the hole mobility and the effect remains for different temperatures. This means that the mobility scattering mechanism is the same, as confirmed in Fig. 3, since both devices present a similar slope. In contrast, the ΔIDS cannot be observed as the strained device presents a higher capacitance equivalent thickness. Moreover, while the IDS in the ON-region raises with the temperature fall, the leakage current reduces due to the thermal activation of the carrier generation in the subthreshold region, as depicted in Fig. 4. On the other hand, the slope for both strained and relaxed devices is different, pointing out that an additional effect also plays a role on the subthreshold swing.[1] S. Takagi et al., ECS Trans., 35(3), 279 (2011). [2] T. Chiarella et al., Solid-State Electron, 54, 855 (2010). [3] A. A. Osman at el, Proc. the 4th Int. High Temp. Electron. Conf., 1998 Fourth International, p. 301 (1998). [4] J. Mitard et al., Tech. Dig., IEEE VLSI (2009), p. 82. Figure 1

We present a review of our recent studies of Bias Temperature Instability (BTI) in Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) fabricated with different material systems, highlighting the reliability opportunities and challenges of each novel device family. We discuss first the intrinsic reliability improvement offered by SiGe and Ge p-channel technologies, if a Si cap is used to passivate the channel, in order to fabricate a standard SiO2/HfO2 gate stack. We focus on SiGe gate stack optimizations for maximum BTI reliability, and on a simple physics-based model able to reproduce the experimental trends. This model framework is then used to understand the suboptimal BTI reliability and excessive time-dependent variability induced by oxide defect charging in different high-mobility channel gate stacks, such as Ge/GeOx/high-k and InGaAs/high-k. Finally we discuss how to pursue a reduction of charge trapping in alternative material systems in order to boost the device reliability and minimize time-dependent variability.

© 2016 IEEE. Ti/p-Ge and NiGe/p-Ge contacts are compared on both planar- and fin-based devices. Ti/p-Ge contacts show low contact resistance, while NiGe/p-Ge devices show short circuit problems due to thermally driven Ni diffusion. Considering the thermal budget in the standard backend of line processing for CMOS, Ti is more suitable for p-Ge devices. A low Ti/p-Ge contact resistivity of 1.1 × 10-8 Ω cm2 is achieved by using a multi-pulse laser annealing technique for B activation. ispartof: IEEE Electron Device Letters vol:37 issue:4 pages:482-485 status: published

Compound semiconductor devices have always intrigued the semiconductor industry due to their high intrinsic mobilities and the heterostructure engineering enabled by those materials. While CMOS has been the vehicle pushing the industry to ever smaller devices, better performance and of course reduced cost, the unique properties of compound semiconductor devices are finding renewed interest in an era where an increasing amount of data is being sent around, stored and analyzed. While several applications like photonics, high-power electronics and image sensors also benefit from enabling a variety of III-V materials and devices, specifically, in the RF Front-End Modules of 5G radio chips [1], these materials allow to address the challenges related to speed, efficiency and output power needed for this next generation wireless communication standard. And while 5G is in full deployment, with first addressing the sub-6GHz frequency bands and in a later phase the mm-wave frequency bands, first publications are already appearing on 6G, where even higher frequencies (beyond > 100GHz) will be targeted [2]. GaN [3] and InP-based devices [4] have a clear performance advantage over Si CMOS and SiGe HBT/BICMOS, but their lower integration potential, still restricted to smaller size substrates and lab-like processing today, is one of the key limitations for adopting those technologies for high-volume 5G and 6G applications. Upscaling those devices to a 200mm/300mm Si platform will be a first step to improve yield and maturity and increase complexity. In a second phase, upscaling and maturing these technologies will allow to co-integrate these devices, usually quite dissimilar to CMOS, with advanced Si technology nodes and provide a fully integrated heterogeneous system. In this talk, we will review the status and progress toward integrating these devices on a CMOS-compatible platform. References [1] N. Collaert et al., "Semiconductor technologies for next generation mobile communications", 14th IEEE International Conference on Solid-State and Integrated Circuit Technology - ICSICT, pp. 1-4, Nov. 2018. [2] White Paper from NTT Docomo regarding 6G, January 2020, [Online]. Available: https://www.nttdocomo.co.jp/english/binary/pdf/corporate/technology/whitepaper_6g/DOCOMO_6G_White_PaperEN_20200124.pdf [3] U. Peralagu et al., “CMOS-compatible GaN-based devices on 200mm-Si for RF applications: integration and performance”, IEDM 2019, pp.398-401. [4] A. Vais et al., “First demonstration of III-V HBTs on 300mm Si substrates using nanoridge technology”, IEDM 2019, pp. 178-181.

With increasing challenges in reducing power density while keeping and even increasing the device performance at every new technology node, innovations in both the device architecture and materials will be needed to ensure continuous improvements in power, performance, area and cost. For the last decade, replacing the Si channel by higher mobility materials like III-V and (Si)Ge has been considered as one of the most challenging innovations needed to further scale down the supply voltage and improve the overall energy efficiency of CMOS circuits. While these materials will not only contribute to enhancing the standard CMOS performance, the possibility of integrating these materials on a Si platform opens exciting new opportunities to build unique circuits, systems and applications. Especially in RF applications, co-integration of III-V/GaN and Si CMOS might be the key enabling technology to provide the speed and power efficiency required for next generation mobile communications. While the device architectures under consideration differ from nowadays ultra-scaled FinFET and nanowire/nanosheet technologies, and their scaling in general is more relaxed, there are significant challenges related to integrating these components on Si substrates. It will need innovations in patterning, deposition and cleaning, next to addressing the challenges of handling these novel materials in a standard CMOS environment. In this work, we will review the status and integration challenges of these materials for both advanced CMOS technologies and RF applications. Focus will be put on the required advancements in etch and deposition needed to enable the integration of these novel materials and devices on a Si platform.

We compare and model the main reliability limitations of stacked Gate-All-Around (GAA) $n$ -/ $p$ -channel Silicon and strained $p$ -channel Germanium Nanowire (NW) transistors. Stress measurements in the entire $\{V_{G},\ V_{D}\}$ space allow to separate the different degradation modes and how they interact with each other. We show that these degradation modes are not universal, as they have a different relative weight depending on the considered technology, and that they can show different acceleration mechanisms. Moreover, we also discuss the impact of self-heating effects (SHE) by means of activation energy extraction in the entire $\{V_{G},\ V_{D}\}$ map.

Nanowires (NW) and nanosheets (NS) are promising channel structure for future technology nodes as they can offer better electrostatics than FinFETs. In this paper, we show another advantage of strained Ge NW pFET over strained Ge FinFET, which lies in the preservation of Strain-Relaxed-Buffer (SRB)-induced strain through fin cut and S/D recess. This benefit comes from the presence of the sacrificial SiGe layers. Lowering the Ge concentration in the SiGe sacrificial layer is a way to further suppress the strain loss. Furthermore, a comparison of Ge NW pFETs integrated on Ge SRB and SiGe SRB reveals that SiGe SRB provides a huge advantage not only in the strain engineering but also in I OFF control. These are key enablers in maximizing the performance while minimizing the I OFF of strained Ge NW pFETs.

3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device density stacking at advanced nodes thanks to the tight alignment precision of the first processed top layer to the last processed bottom layer through the top silicon channel and bonding stack during 193nm immersion lithography. The top devices are junction-less devices fabricated at low temperature $(\mathrm{T}\leq 525^{\circ}\mathrm{C})$ in a top Si layer transferred by wafer-to-wafer bonding with a bonding dielectric stack down to 170nm. The top devices offer similar performance as the high temperature bulk finfet technology for LSTP applications. The use of TiN/TiA1/TiN/HfO 2 gate stack provides the proper threshold voltage adjustment while the insertion of the LaSiO x dipole improves device performance and brings the BTI reliability within specification at low temperature.

An in-depth study of scaled nanowire Ge pFETs for digital and analog applications is proposed. Improved device characteristics are first obtained after gaining a good understanding of the HPA on device performance. Up to 45% higher ID,SAT is obtained at I OFF =3nA/fin when comparing to best Si GAA nFET and similar ID,SAT is found when benchmarking to mature 14/16nm pFinFET technology at −0.5 V DD . The temperature dependent study of I D,SAT highlights that the mechanism limiting the transport in Ge at short channel are neither purely diffusive nor fully ballistic.

3D sequential integration requires top MOSFETs processed at low thermal budget, which can impair the device reliability. In this work, top junction-less device are fabricated with a maximum processing temperature of 525°C. The devices feature high k /metal replacement gate and low temperature Si:P and SiGe:B 60% raised SD for NMOS and PMOS respectively. Device matching, analog and RF performance of the top tier devices are in-line with state-of-the-art Si technology processed at high temperature (>1000°C). The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding.

In this paper, we review the current progress on 3D sequential device stacking, highlighting the main integration challenges and the possible technological solutions. Junction-less devices are shown to be attractive top tier devices for low temperature processing, low complexity of fabrication and meeting reliability specification despite without the use of “reliability” anneal. Next, we explore the potential benefits of 3D sequential stacking at transistor level, CMOS level and for hybrid circuits.

In this work, we will address the opportunities and technology challenges related to next generation mobile communication. To enable the required data rates and reliability for 5G applications, Si CMOS will need to be complemented with new materials and device architectures like III-V or GaN devices to enable at the same time the targeted speed and power efficiency of these systems. Heterogeneous integration, either monolithic or using 3D integration, will be a key enabler to achieve this.

In this paper the Ground Plane (GP) influence on the threshold voltage of Ge pFinFET devices is investigated. In order to explain the experimental threshold voltage variation with fin width, TCAD simulations have been utilized. There are two main process parameters varied in the numerical simulations: a different ground plane peak doping concentration and the distance between the bottom part of the fin and the ground plane. The threshold voltage variation reaches up to 80 mV from the narrowest device to the widest one, for the studied ground plane doping concentration range. Additionally, the slope of the curve of the threshold voltage as a function of channel width varies from 250µV/nm till around 700 µV/nm.

This paper reports on strained p-type Ge Gate-All-Around (GAA) devices on 300mm SiGe Strain-Relaxed-Buffers (SRB) with improved performance as compared to our previous work. The Q factor is increased to 25, I on =500μA/μm at I off =100nA/μm is achieved, approaching the best published results on Ge finFETs. Good NBTI reliability is also maintained. By using the process flow developed for the single nanowire (NW), vertically stacked strained Ge NWs featuring 8nm channel diameter are demonstrated for the first time. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs, demonstrating for the first time 1.7GPa uniaxial-stress along the Ge wire, which originates from the lattice mismatch between the Ge S/D and the Si 0.3 Ge 0.7 SRB.

The floating body retention time is investigated on fully depleted SOI devices with UTBOX. The retention is occurring through the junctions and strongly assisted by defects in the junction space charge region during the holding state at a negative gate voltage. For standard devices with a gate overlap, the junction field is high and the dominant mechanism in this case is the generation by band-to-band tunneling. For optimized extensionless devices with lower junction field, the Shockley–Read–Hall generation enhanced by the field and Poole–Frenkel mechanism takes over the band-to-band tunneling. Therefore, reducing the concentration of Si impurities closer to the junctions is the key to approach an ideal retention time only due to band-to-band tunneling with the Si bandgap as the energy barrier for tunneling.

The self-aligned double patterning scheme has been developed for subtractive Ge fin patterning targeting critical dimension (CD)

In this work, we demonstrate a High-k Metal Gate (HKMG) Implant Free Quantum Well (IFQW) SiGe-pFET device used as a DRAM periphery device. Using a c:Si 0.55 Ge 0.45 channel and embedded e:Si 0.75 Ge 0.25 source/drain (S/D), a very significant source current of 625 μA/μm @ I OFF =100 pA/μm (at supply voltage V DD =−1 V) is demonstrated. The current improvement compared to DRAM compatible unstrained Silicon baseline technology (featuring HKMG) is large, and IFQW transistors are also competitive with regards to Strained Si devices. In particular, IFQW have a specific potential for Sense Amplifiers, with a demonstrated very good drive current/transconductance boost in the range of targeted gate lengths and excellent matching properties.

Single-event transients in SiGe MOS devices with ultrathin quantum well channels have been shown in previous work to exhibit opposite polarities for source and drain strikes. This work reports polarity reversal in similar devices with thick Ge channels due to the favorability of prompt hole collection by either the source or drain region, depending on the strike location. A slower charge-collection mechanism is also present due to the n-well/ p-substrate structure, which allows ion-generated carriers from the substrate to flood the body of the device.