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In this article, a 0.7 nm thick monolayer MoS2 nanosheet gate-all-around field effect transistors (NS-GAAFETs) with conformal high- κ metal gate deposition are demonstrated. The device with 40 nm channel length exhibits a high on-state current density of ~410 μ A μ m−1 with a large on/off ratio of 6 × 108 at drain voltage = 1 V. The extracted contact resistance is 0.48 ± 0.1 kΩ μ m in monolayer MoS2 NS-GAAFETs, thereby showing the channel-dominated performance with the channel length scaling from 80 to 40 nm. The successful demonstration of device performance in this work verifies the integration potential of transition metal dichalcogenides for future logic transistor applications. [ABSTRACT FROM AUTHOR]

Carbon nanotube (CNT) field effect transistors (CNFETs) show promise for the next generation VLSI systems due to their excellent scalability, energy efficiency, and speed. However, high leakage current is a drawback of large diameter CNTs (diameter (DCNT) ≥ 1.4 nm) due to the small electronic band gap (EG) ≤ 0.6 eV and effective mass. This work investigates the on‐current and off‐current tradeoff for two populations of semiconducting‐enriched CNT with DCNT ≈ 1.0 nm displaying a simultaneous 50x improvement in minimun current (IMIN) with 2.5x degradation in contact resistance compared to DCNT ≈ 1.4 nm using a Pd side‐bonded contact. A method to enhance the performance of low‐leakage CNFETs is demonstrated using sub‐monolayer self‐aligned contact doping with 0.8 nm of MoOX, which delivers a 57% reduction in contact resistance to DCNT ≈ 1.0 nm. Robustness is verified after annealing at 200 °C for 30 min and monitoring stability across 6 months post‐fabrication with no change in electrical behaviors. [ABSTRACT FROM AUTHOR]

Semiconducting single‐walled carbon nanotube (CNT) is a promising candidate as a channel material for advanced logic transistors, attributed to the ultra‐thin 1‐nm cylindrical geometry, high mobility, and high carrier injection velocity. However, the presence of undesired CNT bundles in the CNT arrays for wafer‐scale device fabrication, even when utilizing the state‐of‐the‐art dimension‐limited self‐alignment (DLSA) method, poses challenges. These CNT bundles degrade the transistor gate's efficiency in controlling the flow of charge carriers in the CNT channel, leading to pronounced device‐to‐device variability. Here, a novel method is introduced to alleviate bundling in CNT arrays assembled via DLSA, by involving small molecule additive to screen the attractive van der Waals force between neighboring CNTs during the DLSA process, resulting in over 50% reduction in CNT bundling. Furthermore, a pioneering methodology for quantifying CNT bundles is presented and employed experimentally to assess bundles in dense CNT arrays assembled by DLSA using transmission electron microscopy. Both experimental data and molecular dynamics simulation reveal that CNT bundling originates from van der Waals attraction between CNTs, and the disturbed liquid‐liquid interface by accumulating excess polar molecules. These findings illuminate new pathways for realizing dense, bundle‐free CNT arrays. [ABSTRACT FROM AUTHOR]

Ferroelectric properties of individual TiN/Hf0.5Zr0.5O2/TiN capacitors have been measured for technologically relevant areas as small as 60 nm $\times70$ nm, using direct detection of ultralow charge. A crossbar architecture has been utilized to fabricate the ferroelectric capacitors. Switching polarization of $40.1 \mu \text{C}$ /cm $^{2} \ge \text{P}_{\text{sw}} \ge 16.7 \mu \text{C}$ /cm2 and coercive field 1.4 MV/cm $\ge \text{E}_{c} \ge1.09$ MV/cm have been observed for sizes between $1.1 \mu \text{m}$ 2 and 4200 nm2 without discernable trend as function of capacitor size in the present data set. Measured bipolar stress endurance exceeds the maximum measured cycles of 1010 although some capacitors start to show signs of degradation after 109 cycles. A clear correlation between Psw degradation and increased leakage current is observed. The direct measurement of such small area capacitors has been enabled by equipment and circuit design innovations. The present setup allows direct measurement of ferroelectric properties for capacitors as small as 1900 nm2 while further improvements could extend the size limit to 950 nm2 where the design window appears to close. [ABSTRACT FROM AUTHOR]

Proving the device performance and process feasibility is imperative for the realization of two-dimensional (2D) semiconductor electronics. In this work, we have successfully adopted Tin (Sn) as the Ohmic contact metal to monolayer molybdenum disulfide (MoS2) grown by chemical vapor deposition (CVD) and demonstrated superior short channel n-type field effect transistor (nFET) performance reaching an ON-current of $480~\mu \text{A}/\mu \text{m}$ and keeping the OFF-current below 0.1 nA/ $\mu \text{m}$ at $\text{V}_{DS} = 1$ V. These efforts are close to the low power specification of Si transistors in the metrics of International Roadmap for Devices and Systems (IRDS). The performance improvement could be attributed to the re-melting behavior of Sn metal. We suggest that the Sn deposited at lower temperatures could reduce the formation of interfacial defects caused by heat, and high-melting-point capping metal also could assist the re-melting phenomenon of underlying Sn contact layer. These process modifications are helpful to form smooth Sn coverage on MoS2, thereby reducing the contact resistance to 0.84 $\text{k}\Omega \cdot \mu \text{m}$. This work provides a practical pathway to form low-resistance metal contact on 2D semiconductors for performance improvement. [ABSTRACT FROM AUTHOR]

In this article, a 0.7 nm thick monolayer MoS 2 nanosheet gate-all-around field effect transistors (NS-GAAFETs) with conformal high- κ metal gate deposition are demonstrated. The device with 40 nm channel length exhibits a high on-state current density of ~410 μ A μ m -1 with a large on/off ratio of 6 × 10 8 at drain voltage = 1 V. The extracted contact resistance is 0.48 ± 0.1 kΩ μ m in monolayer MoS 2 NS-GAAFETs, thereby showing the channel-dominated performance with the channel length scaling from 80 to 40 nm. The successful demonstration of device performance in this work verifies the integration potential of transition metal dichalcogenides for future logic transistor applications., (© 2024 IOP Publishing Ltd.)