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In the past few years, ever-increasing amounts of image data have been generated by users globally, and these images are routinely stored in cold storage systems in compressed formats. This article investigates the use of approximate storage that leverages the use of cheaper, lower reliability memories that can have higher error rates. Since traditional JPEG-based schemes based on variable-length coding are extremely sensitive to error, the direct use of approximate storage results in severe quality degradation. We propose an error-resilient adaptive-length coding (ALC) scheme that divides all symbols into two classes, based on their frequency of occurrence, where each class has a fixed-length codeword. This provides a balance between the reliability of fixed-length coding schemes, which have a high storage overhead, and the storage-efficiency of Huffman coding schemes, which show high levels of error on low-reliability storage platforms. Further, we use data partitioning to determine which bits are stored in approximate or reliable storage to lower the overall cost of storage. We show that ALC can be used with general non-volatile storage, and can substantially reduce the total cost compared to traditional JPEG-based storage. [ABSTRACT FROM AUTHOR]

In the paradigm of stochastic computing, arithmetic functions are computed on randomized bit streams. The method naturally and effectively tolerates very high clock skew. Exploiting this advantage, this paper introduces polysynchronous clocking, a design strategy in which clock domains are split at a very fine level. Each domain is synchronized by an inexpensive local clock. Alternatively, the skew requirements for a global clock distribution network can be relaxed. This allows for a higher working frequency and so lower latency. The benefits of both approaches are quantified. Polysynchronous clocking results in significant latency, area, and energy savings for wide variety of applications. [ABSTRACT FROM AUTHOR]

Most digital systems operate on a positional representation of data, such as binary radix. An alternative is to operate on random bit streams where the signal value is encoded by the probability of obtaining a one versus a zero. This representation is much less compact than binary radix. However, complex operations can be performed with very simple logic. Furthermore, since the representation is uniform, with all bits weighted equally, it is highly tolerant of soft errors (i.e., bit flips). Both combinational and sequential constructs have been proposed for operating on stochastic bit streams. Prior work has shown that combinational logic can implement multiplication and scaled addition effectively while linear finite-state machines (FSMs) can implement complex functions such as exponentiation and tanh effectively. Prior work on stochastic computation has largely been validated empirically.This paper provides a rigorous mathematical treatment of stochastic implementation of complex functions such as exponentiation and tanh implemented using linear FSMs. It presents two new functions, an absolute value function and exponentiation based on an absolute value, motivated by specific applications. Experimental results show that the linear FSM-based constructs for these functions have smaller area-delay products than the corresponding deterministic constructs. They also are much more tolerant of soft errors. [ABSTRACT FROM AUTHOR]

The throughput degradation of Transport Control Protocol (TCP)/Internet Protocol (IP) networks over lossy links due to the coexistence of congestion losses and link corruption losses is very similar to the degradation of processor performance (i.e., cycle per instruction) due to control hazards in computer design. First, two types of loss events in networks with lossy links are analogous to two possibilities of a branching result in computers (taken vs. not taken). Secondly, both problems result in performance degradations in their applications, i.e., penalties (in clock cycles) in a processor, and throughput degradation (in bits per second) in a TCP/IP network. This has motivated us to apply speculative techniques (i.e., speculating on the outcome of branch predictions), used to overcome control dependencies in a processor, for throughput improvements when lossy links are involved in TCP/IP connections. The objective of this paper is to propose a cross-layer network architecture to improve the network throughput over lossy links. The system consists of protocol-level speculation based algorithms at transport layer, and protocol enhancements at middleware and network layers that provide control and performance parameters to transport layer functions. Simulation results show that, compared with prior research, our proposed system is effective in improving network throughput over lossy links, capable of handling incorrect speculations, fair for other competing flows, backward compatible with legacy networks, and relatively easy to implement. [ABSTRACT FROM AUTHOR]

Abstract: The techniques for fine-grained data sharing are generally available only on specialized architectures, usually involving a shared-bus. The CIRculating Common-Update Sharing (CIRCUS) mechanism has low latency user-level contention-free access to a set of shared circulating data registers. The local access latency is near zero for both read and write operations. These operations can be mapped into more complex operations, such as arithmetic, logical, or data reduction operations such as minimum or sum to be performed by the circulating register hardware (CRH) on the circulating copy of a register. The CRH can also be used to perform atomic operations, such as fetch&add or swap. For a two-dimensional hierarchy of N processing elements (PEs), the write-latency (until the circulating register is updated with a new value) and the update-latency (when all CRH modules can see the updated value) have an optimum cluster size proportional to (N · I/D)1/2, where I is the intercluster time and D is the inter-PE time, including the time between and through one node. The latencies, when optimally clustered, are proportional to (N · I · D)1/2. Sub-microsecond write-latency is expected for up to 15,255 PEs or 660 workstations. For higher levels of hierarchy, the expected write-latency is shown to be proportional to the sum of the latencies of all loop hierarchies. CIRCUS is applicable to a wide variety of system architectures and topologies. [Copyright &y& Elsevier]

Simulators have become an integral part of the computer architecture research and design process. Since they have the advantages of cost, time, and flexibility, architects use them to guide design space exploration and to quantify the efficacy of an enhancement. However, long simulation times and poor accuracy limit their effectiveness. To reduce the simulation time, architects have proposed several techniques that increase the simulation speed or throughput. To increase the accuracy, architects try to minimize the amount of error in their simulators and have proposed adding statistical rigor to their simulation methodology. Since a wide range of approaches exist and since many of them overlap, this paper describes, classifies, and compares them to aid the computer architect in selecting the most appropriate one. [ABSTRACT FROM AUTHOR]

Due to cost, time, and flexibility constraints, computer architects use simulators to explore the design space when developing new processors and to evaluate the performance of potential enhancements. However, despite this dependence on simulators, statistically rigorous simulation methodologies are typically not used in computer architecture research. A formal methodology can provide a sound basis for drawing conclusions gathered from simulation results by adding statistical rigor and, consequently, can increase the architect's confidence in the simulation results. This paper demonstrates the application of a rigorous statistical technique to the setup and analysis phases of the simulation process. Specifically, we apply a Plackett and Burman design to: 1) identify key processor parameters, 2) classify benchmarks based on how they affect the processor, and 3) analyze the effect of processor enhancements. Our results showed that, out of the 41 user-configurable parameters in SimpleScalar, only 10 had a significant effect on the execution time. Of those 10, the number of reorder buffer entries and the L2 cache latency were the two most significant ones, by far. Our results also showed that instruction Precomputation-a value reuse-like microarchitectural technique-primarily improves the processor's performance by relieving integer ALU contention. [ABSTRACT FROM AUTHOR]

Predicting the values that are likely to be produced by instructions has been suggested as a way of increasing the instruction-level parallelism available in a superscalar processor. One of the potential difficulties in cost-effectively predicting values for a given instruction, however, is selecting the proper type of predictor, such as a last-value predictor, a stride predictor, or a context- based predictor. We propose a compiler-directed classification scheme that statically partitions all of the instructions in a program into several groups, each of which is associated with a specific value predictability pattern. This value predictability pattern is encoded into the instructions to identify the type of value predictor that will be best suited for predicting the values that are likely to be produced by each instruction at runtime. Both a profile-based compiler implementation and an implementation based on the 3CC compiler are studied to show the performance bounds for the proposed technique. Our simulations using an extension to the SimpleScalar tool set and the SPEC95 and SPEC2000 benchmark programs indicate that this approach can efficiently use the limited hardware resources in superscalar processors. This static partitioning approach produces better performance than a dynamically partitioned approach and a simple round-robin distribution approach for a given hardware configuration. Finally, this work further demonstrates the connection between value locality behavior and source-level program structures, thereby leading to a deeper understanding of the causes of this behavior. [ABSTRACT FROM AUTHOR]

The fact that instructions in programs often produce repetitive results has motivated researchers to explore various techniques, such as value prediction and value reuse, to exploit this behavior. Value prediction improves the available Instruction-Level Parallelism (ILP) in superscalar processors by allowing dependent instructions to be executed speculatively after predicting the values of their input operands. Value reuse, on the other hand, tries to eliminate redundant computation by storing the previously produced results of instructions and skipping the execution of redundant instructions. Previous value reuse mechanisms use a single instruction or a naturally formed instruction group, such as a basic block, a trace, or a function, as the reuse unit. These naturally-formed instruction groups are readily identifiable by the hardware at runtime without compiler assistance. However, the performance potential of a value reuse mechanism depends on its reuse detection time, the number of reuse opportunities, and the amount of work saved by skipping each reuse unit. Since larger instruction groups typically have fewer reuse opportunities than smaller groups, but they provide greater benefit for each reuse-detection process, it is very important to find the balance point that provides the largest overall performance gain. In this paper, we propose a new mechanism called subblock reuse. Subblocks are created by slicing basic blocks either dynamically or with compiler guidance. The dynamic approaches use the number of instructions, numbers of inputs and outputs, or the presence of store instructions to determine the subblock boundaries. The compiler-assisted approach slices basic blocks using data-flow considerations to balance the reuse granularity and the number of reuse opportunities. The results show that subblocks, which can produce up to 36 percent speedup if reused properly, are better candidates for reuse units than basic blocks. Although subblock reuse with... [ABSTRACT FROM AUTHOR]

Examines the course-grained thread pipelining, a speculative parallel execution model, for shared-memory multiprocessors. Influence of the pipelined execution of loop iterations in producing low parallelization overhead; Use of the synthetic benchmarks in evaluating the performance of the model; Impact of the model on the speedup of programs.

Presents a course on computer systems performance analysis for continuing education which has been adapted for distance education delivery options in Minnesota. Drop-out rate for remote and on-campus students; Preference for face-to-face instruction; Topics covered in typical offering of course; Completion rate for each category of student enrollment.

The expanding gap between microprocessor and DRAM performance has necessitated the use of increasingly aggressive techniques designed to reduce or hide the latency of main memory access. Although large cache hierarchies have proven to be effective in reducing this latency for the most frequently used data, it is still not uncommon for many programs to spend more than half their run times stalled on memory requests. Data prefetching has been proposed as a technique for hiding the access latency of data referencing patterns that defeat caching strategies. Rather than waiting for a cache miss to initiate a memory fetch, data prefetching anticipates such misses and issues a fetch to the memory system in advance of the actual memory reference. To be effective, prefetching must be implemented in such a way that prefetches are timely, useful, and introduce little overhead. Secondary effects such as cache pollution and increased memory bandwidth requirements must also be taken into consideration. Despite these obstacles, prefetching has the potential to significantly improve overall program execution time by overlapping computation with memory accesses. Prefetching strategies are diverse, and no single strategy has yet been proposed that provides optimal performance. The following survey examines several alternative approaches, and discusses the design tradeoffs involved when implementing a data prefetch strategy. [ABSTRACT FROM AUTHOR]

Provides information on a study which examined the input and output value locality of basic blocks to determine their predictability and their potential for reuse. Information on the input and output value locality of basic blocks; Performance potential of basic block reuse; Impact of compiler optimizations; Conclusion.

Presents a study which suggested that using compiler support to extend value reuse to a coarser granularity may have performance benefits. Impact of compiler optimizations; Conclusion.

Discusses performance-based path determination for interprocessor communication in distributed computing systems. Technique in exploiting multiple heterogeneous communication networks that interconnect the same set of processing nodes; Performance-based path selection and path aggregation; Testing of the techniques; Network computing and characteristics.

Due to data spreading among processors and due to the cache coherence problem, private data caches have not been as effective in reducing the average memory delay in multiprocessors as in uniprocessors. A wide variety of mechanisms have been proposed for maintaining cache coherence in large-scale shared-memory multiprocessors, making it difficult to compare their performance and implementation implications. To help the computer architect understand some of the trade-offs involved, this paper surveys current cache coherence mechanisms and identifies several issues critical to their design. These design issues include: (1) the coherence detection strategy, through which possibly incoherent memory accesses are detected either statically at compile-time, or dynamically at run-time; (2) the coherence enforcement strategy, such as updating or invalidating, used to ensure that stale cache entries are never referenced by a processor; (3) how the precision of block-sharing information can be changed to trade-off the implementation cost and performance of the coherence mechanism; and (4) how the cache block size affects the performance of the memory system. Trace-driven simulations are used to compare the performance and implementation impacts of these different issues. Additionally, hybrid strategies are presented that can enhance the performance of the multiprocessor memory system by combining several different coherence mechanisms into a single system. [ABSTRACT FROM AUTHOR]

Presents an alternative processor allocation technique called Loop-Level Process Control (LLPC). How the LLPC works; What is it based on; Evaluation of the LLPC's performance on a Silicon Graphics Challenge multiprocessor system; Significant improvements shown over traditional time-sharing and gang-scheduling.

Discusses data prefetching techniques for reducing computer memory access latency. Advantages over the use of cache memory hierarchies; Enhancement of performance of some scientific applications running on commercial systems; Software prefetching; Hardware prefetching; Reference prediction table. INSET: Prefetching in the HP PA-RISC family..

Background: There are few studies on the differences in end‐of‐life decisions making in critically ill patients with and without coronavirus disease 2019 (COVID‐19). This study aimed to investigate the independent factors that predicted the decision to withdraw or withhold life‐sustaining treatments (LST) in critically ill patients and if these decisions were based on different variables for critically ill patients with COVID‐19 compared to those for critically ill patients with other diagnoses in a Swedish intensive care unit. Methods: This observational pilot study was performed at Sahlgrenska University Hospital, Gothenburg, Sweden. Patients ≥65 years were included from 1 March 2020 to 30 April 2021. The association between a decision to limit LST and a priori selected variables including sex, age, Simplified Acute Physiology Score 3 (SAPS 3), Clinical Frailty Scale ≥4, Charlson Comorbidity Index, Body Mass Index, living at home, invasive and non‐invasive mechanical ventilation was assessed using a univariate and multivariable logistic regression model and presented as odds ratio with corresponding 95% confidence intervals. Results: There were 394 patients included in this study, 131 in the non‐COVID‐19 group and 263 in the COVID‐19 group. For the non‐COVID‐19 cohort, the univariate analysis demonstrated that age and SAPS 3 were significantly associated with the decision to withdraw or withhold life‐sustaining treatments, and this association remained in the multivariable analysis, with odds ratios of 1.10 (1.03–1.19) p =.009 and 1.06 (1.03–1.10) p <.001, respectively. For the COVID‐19 cohort, the univariate analysis indicated that age, SAPS 3, and Charlson comorbidity index were significantly associated with the decision to withdraw or withhold life‐sustaining treatments. However, in multivariable analysis, only the Charlson comorbidity index remained independently associated with the decision to withdraw or withhold life‐sustaining treatments, with an odds ratio of 1.26 (1.07–1.49), p =.006. Conclusion: Decisions to withdraw or withhold life‐sustaining treatments were based on other variables for the critically ill COVID‐19 cohort compared to those for the critically ill non‐COVID‐19 cohort. Further studies are warranted to forge a common path for ethical end‐of‐life decision‐making in critically ill patients. [ABSTRACT FROM AUTHOR]

The article discusses various articles published within the issue including "Performance Models of Storage Contention in Cloud Environments," "Performance Modeling and Analysis of Message-oriented Event-driven Systems," and "Experience with Model-based Performance, Reliability and Adaptability Assessment of a Complex Industrial Architecture."

Computing on time-based data is a recent evolution of research in stochastic computing. As with stochastic computing, complex functions can be computed with remarkably low area cost. Unlike stochastic computing, the latency and energy efficiency are very favorable compared to computations on conventional binary radix. In this article, the authors review and evaluate the design and implementation of arithmetic operations on time-encoded signals, with a particular focus on low power. The advantages, challenges, and potential applications are discussed. [ABSTRACT FROM AUTHOR]

Spintronic memory [spin‐transfer torque‐magnetic random access memory (STT‐MRAM)] is an attractive alternative technology to CMOS since it offers higher density and virtually no leakage current. Spintronic memory continues to require higher write energy, however, presenting a challenge to memory hierarchy design when energy consumption is a concern. This study motivates the use of STT‐MRAM for the first‐level caches of a multicore processor to reduce energy consumption without significantly degrading the performance. The large STT‐MRAM first‐level cache implementation saves leakage power. Moreover, the use of small level‐0 cache regains the performance drop due to STT‐MRAM long write latencies. The combination of both reduces the energy‐delay product by 65% on average compared with CMOS baseline. The proposed STT hierarchy also shows good scalability over the CMOS with a few benchmarks which scale significantly better. The PARSEC and Splash2 benchmark suites are analysed running on a modern multicore platform, comparing performance, energy consumption and scalability of the spintronic cache system to a CMOS design. [ABSTRACT FROM AUTHOR]

Due to the long simulation time of the reference input set, computer architects often use reduced time simulation techniques to shorten the simulation time. However, what has not yet been thoroughly evaluated is the accuracy of these techniques relative to the reference input set and with respect to each other. To rectify this deficiency, this paper uses three methods to characterize reduced input set, truncated execution, and sampling-based simulation techniques while also examining their speed versus accuracy trade-off and configuration dependence. Our results show that the three sampling-based techniques, SimPoint, SMARTS, and random sampling, have the best accuracy, the best speed versus accuracy trade-off, and the least configuration dependence. On the other hand, the reduced input set and truncated execution simulation techniques had generally poor accuracy, were not significantly faster than the sampling-based techniques, and were severely configuration dependent. The final contribution of this paper is a decision tree, which can help architects choose the most appropriate technique for their simulations. [ABSTRACT FROM AUTHOR]

The authors reflect on the future of the simulation technology in the computer industry. Researchers have resorted to simulators to model system behavior, and have generated quantitative estimates of expected performance due to the enormous complexity of computer systems. They argue that simulators are the most important tools for computer architecture researchers since simulators offer a balance of cost, timeliness, and flexibility.

With the convergence of wireless communication and IP-based networking technologies, future IP-based wireless networks are expected to support real-time multimedia. IP services over wireless networks (e.g. wireless access to Internet) enhance the mobility and flexibility of traditional IP network users. Wireless networks extend the current IP service infrastructure to a mix of transmission media, bandwidth, costs, coverage, and service agreements, requiring enhancements to the IP protocol layers in wireless networks. Furthermore, QoS provisioning is required at various layers of the IP protocol stack to guarantee different types of service requests, giving rise to issues related to cross-layer design methodology. This paper reviews issues and prevailing solutions to performance enhancements and QoS provisioning for IP services over mobile wireless networks from a layered view. Copyright © 2006 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

The speculated execution of threads in a multithreaded architecture, plus the branch prediction used in each thread execution unit, allows many instructions to be executed speculatively, that is, before it is known whether they actually will be needed by the program. In this study, we examine how the load instructions executed on what turn out to be incorrectly executed program paths impact the memory system performance. We find that incorrect speculation (wrong execution) on the instruction and thread-level provides an indirect prefetching effect for the later correct execution paths and threads. By continuing to execute the mispredicted load instructions even after the instruction or thread-level control speculation is known to be incorrect, the cache misses observed on the correctly executed paths can be reduced by 16 to 73 percent, with an average reduction of 45 percent. However, we also find that these extra loads can increase the amount of memory traffic and can pollute the cache. We introduce the small, fully associative Wrong Execution Cache (WEC) to eliminate the potential pollution that can be caused by the execution of the mispredicted load instructions. Our simulation results show that the WEC can improve the performance of a concurrent multithreaded architecture up to 18.5 percent on the benchmark programs tested, with an average improvement of 9.7 percent, due to the reductions in the number of cache misses. [ABSTRACT FROM AUTHOR]

Stochastic computing (SC) is a promising technology that can be used for low-cost hardware designs. However, SC suffers from its long latency. Although parallel processing can efficiently shorten the latency, duplicated stochastic number generators (SNGs) are necessary, which cause substantial hardware overhead. This paper proposes a scalable SNG based on the spin-Hall-effect (SHE), which is capable of generating multiple independent stochastic streams simultaneously. The design takes advantages of the efficient charge-to-spin conversion from the Spin-Hall material and the intrinsic stochasticity of nanomagnets. Compared to previous spintronic SNGs, the SHE-SNG can reduce the area by $1.6\times -7.8\times $ and the power by $4.9\times -13\times $ while increasing the degree of parallelism from 1 to 16. Compared to CMOS-based SNGs, the proposed SNG obtained $24\times -120\times $ and $53\times $ reduction in terms of area and power, respectively. Finally, three benchmarks were implemented, and the results indicate that SC implementations with the proposed SHE-SNG can achieve $1.2\times -29\times $ reduction of hardware resources compared to implementations with previous CMOS- and spintronic-based designs while scaling the degree of parallelism from 1 to 64. [ABSTRACT FROM AUTHOR]

Approximate computing has gained research attention recently as a way to increase energy efficiency and/or performance by exploiting some applications' intrinsic error resiliency. However, little attention has been given to its potential for tackling the communication bottleneck that remains one of the looming challenges to be tackled for efficient parallelism. This article explores the potential benefits of approximate computing for communication reduction by surveying three promising techniques for approximate communication: compression, relaxed synchronization, and value prediction. The techniques are compared based on an evaluation framework composed of communication cost reduction, performance, energy reduction, applicability, overheads, and output degradation. Comparison results demonstrate that lossy link compression and approximate value prediction show great promise for reducing the communication bottleneck in bandwidth-constrained applications. Meanwhile, relaxed synchronization is found to provide large speedups for select error-tolerant applications, but suffers from limited general applicability and unreliable output degradation guarantees. Finally, this article concludes with several suggestions for future research on approximate communication techniques. [ABSTRACT FROM AUTHOR]

A novel digitally driven pixel circuit for active-matrix organic light-emitting diode (OLED) microdisplays is proposed and evaluated. This circuit supports both pulse width modulation and pulse density modulation digital drive approaches. Only three transistors and one capacitor are required per pixel for the proposed circuit. A current mirror is used to compensate for the pixel current changes that occur because of the degradation of the OLEDs over time. The compensation current depends on the potential of the common cathode, the properties of the current mirror, and the Width/Length ( W/ L) ratio of the drive transistor. The proposed digital pixel circuit also has advantages in circuit layout compared with analog pixel circuits. [ABSTRACT FROM AUTHOR]

We investigated magnetic tunnel junction (MTJ)-based circuit that allows direct communication between elements without intermediate sensing amplifiers. Two- and three-input circuits that consist of two and three MTJs connected in parallel, respectively, were fabricated and are compared. The direct communication is realized by connecting the output in series with the input and applying voltage across the series connections. The logic circuit relies on the fact that a change in resistance at the input modulates the voltage that is needed to supply the critical current for spin-transfer torque switching the output. The change in the resistance at the input resulted in a voltage swing of 50–200 mV and 250–300 mV for the closest input states for the three and two input designs, respectively. The two input logic gate realizes the AND, NAND, NOR, and OR logic functions. The three-input logic function realizes the majority, AND, NAND, NOR, and OR logic operations. [ABSTRACT FROM AUTHOR]

Abstract: Many complex natural systems studied in the geosciences are characterized by simple local-scale interactions that result in complex emergent behavior. Simulations of these systems, often implemented in parallel using standard central processing unit (CPU) clusters, may be better suited to parallel processing environments with large numbers of simple processors. Such an environment is found in graphics processing units (GPUs) on graphics cards. This paper discusses GPU implementations of three example applications from computational fluid dynamics, seismic wave propagation, and rock magnetism. These candidate applications involve important numerical modeling techniques, widely employed in physical system simulations, that are themselves examples of distinct computing classes identified as fundamental to scientific and engineering computing. The presented numerical methods (and respective computing classes they belong to) are: (1) a lattice-Boltzmann code for geofluid dynamics (structured grid class); (2) a spectral-finite-element code for seismic wave propagation simulations (sparse linear algebra class); and (3) a least-squares minimization code for interpreting magnetic force microscopy data (dense linear algebra class). Significant performance increases (between 10 and 30 in most cases) are seen in all three applications, demonstrating the power of GPU implementations for these types of simulations and, more generally, their associated computing classes. [Copyright &y& Elsevier]

Discusses recommendations made by a group of researchers to the U.S. National Science Foundation regarding the experimental and evaluation problems faced by processor architecture research. Problems posed by the ways in which existing simulation infrastructures are written; Benchmarking problems; Metrics, evaluation accuracy, and validation.

This survey describes research directions in techniques to improve the performance of programs written in the Java programming language. The standard technique for Java execution is interpretation, which provides for extensive portability of programs. A Java interpreter dynamically executes Java bytecodes, which comprise the instruction set of the Java Virtual Machine (JVM). Execution time performance of Java programs can be improved through compilation, possibly at the expense of portability. Various types of Java compilers have been proposed, including Just-In-Time (JIT) compilers that compile bytecodes into native processor instructions on the fly; direct compilers that directly translate the Java source code into the target processor's native language; and bytecode-to-source translators that generate either native code or an intermediate language, such as C, from the bytecodes. Additional techniques, including bytecode optimization, dynamic compilation, and executing Java programs in parallel, attempt to improve Java run-time performance while maintaining Java's portability. Another alternative for executing Java programs is a Java processor that implements the JVM directly in hardware. In this survey, we discuss the basic features, and the advantages and disadvantages, of the various Java execution techniques. We also discuss the various Java benchmarks that are being used by the Java community for performance evaluation of the different techniques. Finally, we conclude with a comparison of the performance of the alternative Java execution techniques based on reported results. [ABSTRACT FROM AUTHOR]

The Java Trademark programming language, with its portability, object-oriented model, support for multithreading and distributed programming, and garbage collection features, is becoming the language of choice for the development of large-scale distributed applications. Without a suitable performance analysis tool for Java programs, however, it is often difficult to analyze the programs for performance-tuning problems. The profiler included in Sun's Java Development Kit (JDK Trademark) 1.1 does not provide sufficiently detailed trace information to address performance issues in large applications. Also, it does not support the tracing of client/server applications, which are very important for analyzing distributed systems. The JaViz performance analysis tool generates execution traces with sufficient detail to determine program hot spots, including remote method calls, in a distributed Java application program. JaViz provides a graphical display of the program execution tree for the entire distributed application in the form of a call graph for ease of visualization. A number of features allow users to analyze the execution tree for performance-tuning problems more easily than other Java performance monitoring tools. The usability and functionality of the JaViz tool set is demonstrated by applying it to an example distributed Java application program. [ABSTRACT FROM AUTHOR]

The electrical and physical properties of pure single-walled carbon nanotube thin films deposited through a layer-by-layer-self-assembly process are discussed. The film thickness was proportional to the number of dipping cycles. The film resistivity was estimated as 2.19×10-3 Ω cm after thermal treatment processes were performed. The estimated specific contact resistance to gold electrodes was 6.33×10-9 Ω m2 from contact chain measurements. The fabricated three-terminal microelectromechanical switch using these films functioned as a beam for multiple switching cycles with a 4.5 V pull-in voltage. This switch is believed to be a promising device for low power digital logic applications. [ABSTRACT FROM AUTHOR]

We experimentally demonstrated a magnetic tunnel junction (MTJ) based circuit that allows direct communication between elements without intermediate sensing amplifiers. The input of the circuit consists of three MTJs connected in parallel. The direct communication is realized by connecting the output in series with the input and applying voltage across the series connections. Combining the circuit with complementary metal oxide semiconductor current mirrors allows for fan-out to multiple outputs. The change in resistance at the input resulted in a voltage swing across the output of 150-200 mV for the closest input states which is sufficient to realize all of the Boolean primitives. [ABSTRACT FROM AUTHOR]

Mounting concerns over variability, defects, and noise motivate a new approach for digital circuitry: stochastic logic, that is to say, logic that operates on probabilistic signals and so can cope with errors and uncertainty. Techniques for probabilistic analysis of circuits and systems are well established. We advocate a strategy for synthesis. In prior work, we described a methodology for synthesizing stochastic logic, that is to say logic that operates on probabilistic bit streams. In this paper, we apply the concept of stochastic logic to a reconfigurable architecture that implements processing operations on a datapath. We analyze cost as well as the sources of error: approximation, quantization, and random fluctuations. We study the effectiveness of the architecture on a collection of benchmarks for image processing. The stochastic architecture requires less area than conventional hardware implementations. Moreover, it is much more tolerant of soft errors (bit flips) than these deterministic implementations. This fault tolerance scales gracefully to very large numbers of errors. [ABSTRACT FROM AUTHOR]