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Fault-tolerant quantum computation relies on the assumption of time-invariant, sufficiently low physical error rates. However, current superconducting quantum computers suffer from frequent disruptive noise events, including cosmic ray impacts and shifting two-level system defects. Several methods have been proposed to mitigate these issues in software, but they add large overheads in terms of physical qubit count, as it is difficult to preserve logical information through burst error events. We focus on mitigating multi-qubit burst errors in magic state factories, which are expected to comprise up to 95% of the space cost of future quantum programs. Our key insight is that magic state factories do not need to preserve logical information over time; once we detect an increase in local physical error rates, we can simply turn off parts of the factory that are affected, re-map the factory to the new chip geometry, and continue operating. This is much more efficient than previous more general methods, and is resilient even under many simultaneous impact events. Using precise physical noise models, we show an efficient ray detection method and evaluate our strategy in different noise regimes. Compared to existing baselines, we find reductions in ray-induced overheads by several orders of magnitude, reducing total qubitcycle cost by geomean 6.5x to 13.9x depending on the noise model. This work reduces the burden on hardware by providing low-overhead software mitigation of these errors., Comment: 13 pages, 12 figures

Running quantum algorithms protected by quantum error correction requires a real time, classical decoder. To prevent the accumulation of a backlog, this decoder must process syndromes from the quantum device at a faster rate than they are generated. Most prior work on real time decoding has focused on an isolated logical qubit encoded in the surface code. However, for surface code, quantum programs of utility will require multi-qubit interactions performed via lattice surgery. A large merged patch can arise during lattice surgery -- possibly as large as the entire device. This puts a significant strain on a real time decoder, which must decode errors on this merged patch and maintain the level of fault-tolerance that it achieves on isolated logical qubits. These requirements are relaxed by using spatially parallel decoding, which can be accomplished by dividing the physical qubits on the device into multiple overlapping groups and assigning a decoder module to each. We refer to this approach as spatially parallel windows. While previous work has explored similar ideas, none have addressed system-specific considerations pertinent to the task or the constraints from using hardware accelerators. In this work, we demonstrate how to configure spatially parallel windows, so that the scheme (1) is compatible with hardware accelerators, (2) supports general lattice surgery operations, (3) maintains the fidelity of the logical qubits, and (4) meets the throughput requirement for real time decoding. Furthermore, our results reveal the importance of optimally choosing the buffer width to achieve a balance between accuracy and throughput -- a decision that should be influenced by the device's physical noise.

Despite the necessity of fault-tolerant quantum sys- tems built on error correcting codes, many popular codes, such as the surface code, have prohibitively large qubit costs. In this work we present a protocol for efficiently implementing a restricted set of space-efficient quantum error correcting (QEC) codes in atom arrays. This protocol enables generalized-bicycle codes that require up to 10x fewer physical qubits than surface codes. Additionally, our protocol enables logical cycles that are 2-3x faster than more general solutions for implementing space- efficient QEC codes in atom arrays. We also evaluate a proof-of-concept quantum memory hier- archy where generalized-bicycle codes are used in conjunction with surface codes for general computation. Through a detailed compilation methodology, we estimate the costs of key fault- tolerant benchmarks in a hierarchical architecture versus a state-of-the-art surface code only architecture. Overall, we find the spatial savings of generalized-bicycle codes outweigh the overhead of loading and storing qubits, motivating the feasibility of a quantum memory hierarchy in practice. Through sensitivity studies, we also identify key program-level and hardware-level features for using a hierarchical architecture.

Unitary t-designs are distributions on the unitary group whose first t moments appear maximally random. Previous work has established several upper bounds on the depths at which certain specific random quantum circuit ensembles approximate t-designs. Here we show that these bounds can be extended to any fixed architecture of Haar-random two-site gates. This is accomplished by relating the spectral gaps of such architectures to those of 1D brickwork architectures. Our bound depends on the details of the architecture only via the typical number of layers needed for a block of the circuit to form a connected graph over the sites. When this quantity is independent of width, the circuit forms an approximate t-design in linear depth. We also give an implicit bound for nondeterministic architectures in terms of properties of the corresponding distribution over fixed architectures., Comment: 29 pages, 8 figures

In order to achieve error rates necessary for advantageous quantum algorithms, Quantum Error Correction (QEC) will need to be employed, improving logical qubit fidelity beyond what can be achieved physically. As today's devices begin to scale, co-designing architectures for QEC with the underlying hardware will be necessary to reduce the daunting overheads and accelerate the realization of practical quantum computing. In this work, we focus on logical computation in QEC. We address quantum computers made from neutral atom arrays to design a surface code architecture that translates the hardware's higher physical connectivity into a higher logical connectivity. We propose groups of interleaved logical qubits, gaining all-to-all connectivity within the group via efficient transversal CNOT gates. Compared to standard lattice surgery operations, this reduces both the overall qubit footprint and execution time, lowering the spacetime overhead needed for small-scale QEC circuits. We also explore the architecture's scalability. We look at using physical atom movement schemes and propose interleaved lattice surgery which allows an all-to-all connectivity between qubits in adjacent interleaved groups, creating a higher connectivity routing space for large-scale circuits. Using numerical simulations, we evaluate the total routing time of interleaved lattice surgery and atom movement for various circuit sizes. We identify a cross-over point defining intermediate-scale circuits where atom movement is best and large-scale circuits where interleaved lattice surgery is best. We use this to motivate a hybrid approach as devices continue to scale, with the choice of operation depending on the routing distance.

Noisy Intermediate-Scale Quantum Computing (NISQ) has dominated headlines in recent years, with the longer-term vision of Fault-Tolerant Quantum Computation (FTQC) offering significant potential albeit at currently intractable resource costs and quantum error correction (QEC) overheads. For problems of interest, FTQC will require millions of physical qubits with long coherence times, high-fidelity gates, and compact sizes to surpass classical systems. Just as heterogeneous specialization has offered scaling benefits in classical computing, it is likewise gaining interest in FTQC. However, systematic use of heterogeneity in either hardware or software elements of FTQC systems remains a serious challenge due to the vast design space and variable physical constraints. This paper meets the challenge of making heterogeneous FTQC design practical by introducing HetArch, a toolbox for designing heterogeneous quantum systems, and using it to explore heterogeneous design scenarios. Using a hierarchical approach, we successively break quantum algorithms into smaller operations (akin to classical application kernels), thus greatly simplifying the design space and resulting tradeoffs. Specializing to superconducting systems, we then design optimized heterogeneous hardware composed of varied superconducting devices, abstracting physical constraints into design rules that enable devices to be assembled into standard cells optimized for specific operations. Finally, we provide a heterogeneous design space exploration framework which reduces the simulation burden by a factor of 10^4 or more and allows us to characterize optimal design points. We use these techniques to design superconducting quantum modules for entanglement distillation, error correction, and code teleportation, reducing error rates by 2.6x, 10.7x, and 3.0x compared to homogeneous systems.

Fabrication errors pose a significant challenge in scaling up solid-state quantum devices to the sizes required for fault-tolerant (FT) quantum applications. To mitigate the resource overhead caused by fabrication errors, we combine two approaches: (1) leveraging the flexibility of a modular architecture, (2) adapting the procedure of quantum error correction (QEC) to account for fabrication defects. We simulate the surface code adapted to qubit arrays with arbitrarily distributed defects to find metrics that characterize how defects affect fidelity. We then determine the impact of defects on the resource overhead of realizing a fault-tolerant quantum computer, on a chiplet-based modular architecture. Our strategy for dealing with fabrication defects demonstrates an exponential suppression of logical failure where error rates of non-faulty physical qubits are ~0.1% in a circuit-based noise model. This is a typical regime where we imagine running the defect-free surface code. We use our numerical results to establish post-selection criteria for building a device from defective chiplets. Using our criteria, we then evaluate the resource overhead in terms of the average number of fabricated physical qubits per logical qubit. We find that an optimal choice of chiplet size, based on the defect rate and target fidelity, is essential to limiting any additional error correction overhead due to defects. When the optimal chiplet size is chosen, at a defect rate of 1% the resource overhead can be reduced to below 3X and 6X respectively for the two defect models we use, for a wide range of target performance. We also determine cutoff fidelity values that help identify whether a qubit should be disabled or kept as part of the error correction code., Comment: In ASPLOS 2024: the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

We test grip strength and shock absorption properties of various granular material in granular jamming robotic components. The granular material comprises a range of natural, manufactured, and 3D printed material encompassing a wide range of shapes, sizes, and Shore hardness. Two main experiments are considered, both representing compelling use cases for granular jamming in soft robotics. The first experiment measures grip strength (retention force measured in Newtons) when we fill a latex balloon with the chosen grain type and use it as a granular jamming gripper to pick up a range of test objects. The second experiment measures shock absorption properties recorded by an Inertial Measurement Unit which is suspended in an envelope of granular material and dropped from a set height. Our results highlight a range of shape, size and softness effects, including that grain deformability is a key determinant of grip strength, and interestingly, that larger grain sizes in 3D printed grains create better shock absorbing materials.

We develop general purpose algorithms for computing and utilizing both the Dyson series and Magnus expansion, with the goal of facilitating numerical perturbative studies of quantum dynamics. To enable broad applications to models with multiple parameters, we phrase our algorithms in terms of multivariable sensitivity analysis, for either the solution or the time-averaged generator of the evolution over a fixed time-interval. These tools simultaneously compute a collection of terms up to arbitrary order, and are general in the sense that the model can depend on the parameters in an arbitrary time-dependent way. We implement the algorithms in the open source software package \qiskitdynamics{}, utilizing the JAX array library to enable just-in-time compilation, automatic differentiation, and GPU execution of all computations. Using a model of a single transmon, we demonstrate how to use these tools to approximate fidelity in a region of model parameter space, as well as construct perturbative robust control objectives. We also derive and implement Dyson and Magnus-based variations of the recently introduced Dysolve algorithm [Shillito et al., Physical Review Research, 3(3):033266] for simulating linear matrix differential equations. We show how the pre-computation step can be phrased as a multivariable expansion computation problem with fewer terms than in the original method. When simulating a two-transmon entangling gate on a GPU, we find the Dyson and Magnus-based solvers provide a speedup over traditional ODE solvers, ranging from roughly $2\times$ to $4\times$ for a solution and $10\times$ to $60\times$ for a gradient, depending on solution accuracy., Comment: Accepted version: Speedup results updated after rerunning simulations with updated packages, modified figures, and expanded discussions

Near-term quantum computers are primarily limited by errors in quantum operations (or gates) between two quantum bits (or qubits). A physical machine typically provides a set of basis gates that include primitive 2-qubit (2Q) and 1-qubit (1Q) gates that can be implemented in a given technology. 2Q entangling gates, coupled with some 1Q gates, allow for universal quantum computation. In superconducting technologies, the current state of the art is to implement the same 2Q gate between every pair of qubits (typically an XX- or XY-type gate). This strict hardware uniformity requirement for 2Q gates in a large quantum computer has made scaling up a time and resource-intensive endeavor in the lab. We propose a radical idea -- allow the 2Q basis gate(s) to differ between every pair of qubits, selecting the best entangling gates that can be calibrated between given pairs of qubits. This work aims to give quantum scientists the ability to run meaningful algorithms with qubit systems that are not perfectly uniform. Scientists will also be able to use a much broader variety of novel 2Q gates for quantum computing. We develop a theoretical framework for identifying good 2Q basis gates on "nonstandard" Cartan trajectories that deviate from "standard" trajectories like XX. We then introduce practical methods for calibration and compilation with nonstandard 2Q gates, and discuss possible ways to improve the compilation. To demonstrate our methods in a case study, we simulated both standard XY-type trajectories and faster, nonstandard trajectories using an entangling gate architecture with far-detuned transmon qubits. We identify efficient 2Q basis gates on these nonstandard trajectories and use them to compile a number of standard benchmark circuits such as QFT and QAOA. Our results demonstrate an 8x improvement over the baseline 2Q gates with respect to speed and coherence-limited gate fidelity., Comment: In MICRO 2022: 55th IEEE/ACM International Symposium on Microarchitecture, 17 pages, 7 figures

The overheads of classical decoding for quantum error correction on superconducting quantum systems grow rapidly with the number of logical qubits and their correction code distance. Decoding at room temperature is bottle-necked by refrigerator I/O bandwidth while cryogenic on-chip decoding is limited by area/power/thermal budget. To overcome these overheads, we are motivated by the observation that in the common case, error signatures are fairly trivial with high redundancy/sparsity, since the error correction codes are over-provisioned to correct for uncommon worst-case complex scenarios (to ensure substantially low logical error rates). If suitably exploited, these trivial signatures can be decoded and corrected with insignificant overhead, thereby alleviating the bottlenecks described above, while still handling the worst-case complex signatures by state-of-the-art means. Our proposal, targeting Surface Codes, consists of: 1) Clique: A lightweight decoder for decoding and correcting trivial common-case errors, designed for the cryogenic domain. The decoder is implemented for SFQ logic. 2) A statistical confidence-based technique for off-chip decoding bandwidth allocation, to efficiently handle rare complex decodes which are not covered by the on-chip decoder. 3) A method for stalling circuit execution, for the worst-case scenarios in which the provisioned off-chip bandwidth is insufficient to complete all requested off-chip decodes. In all, our proposal enables 70-99+% off-chip bandwidth elimination across a range of logical and physical error rates, without significantly sacrificing the accuracy of state-of-the-art off-chip decoding. By doing so, it achieves 10-10000x bandwidth reduction over prior off-chip bandwidth reduction techniques. Furthermore, it achieves a 15-37x resource overhead reduction compared to prior on-chip-only decoding., Comment: To appear at the 28th Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2023)

The application of granular jamming in soft robotics is a recent and promising new technology offer exciting possibilities for creating higher performance robotic devices. Granular jamming is achieved via the application of a vacuum pressure inside a membrane containing particulate matter, and is particularly interesting from a design perspective, as a myriad of design parameters can potentially be exploited to induce a diverse variety of useful behaviours. To date, the effect of variables such as grain shape and size, as well as membrane material, have been studied as a means of inducing bespoke gripping performance, however the other main contributing factor, membrane morphology, has not been studied due to its particular complexities in both accurate modelling and fabrication. This research presents the first study that optimises membrane morphology for granular jamming grippers, combining multi-material 3D printing and an evolutionary algorithm to search through a varied morphology design space in materio. Entire generations are printed in a single run and gripper retention force is tested and used as a fitness measure. Our approach is relatively scalable, circumvents the need for modelling, and guarantees the real-world performance of the grippers considered. Results show that membrane morphology is a key determinant of gripper performance. Common high performance designs are seen to optimise all three of the main identified mechanisms by which granular grippers generate grip force, are significantly different from a standard gripper morphology, and generalise well across a range of test objects., Comment: 8 pages

One of the key challenges in current Noisy Intermediate-Scale Quantum (NISQ) computers is to control a quantum system with high-fidelity quantum gates. There are many reasons a quantum gate can go wrong -- for superconducting transmon qubits in particular, one major source of gate error is the unwanted crosstalk between neighboring qubits due to a phenomenon called frequency crowding. We motivate a systematic approach for understanding and mitigating the crosstalk noise when executing near-term quantum programs on superconducting NISQ computers. We present a general software solution to alleviate frequency crowding by systematically tuning qubit frequencies according to input programs, trading parallelism for higher gate fidelity when necessary. The net result is that our work dramatically improves the crosstalk resilience of tunable-qubit, fixed-coupler hardware, matching or surpassing other more complex architectural designs such as tunable-coupler systems. On NISQ benchmarks, we improve worst-case program success rate by 13.3x on average, compared to existing traditional serialization strategies.

We introduce the French Street Name Signs (FSNS) Dataset consisting of more than a million images of street name signs cropped from Google Street View images of France. Each image contains several views of the same street name sign. Every image has normalized, title case folded ground-truth text as it would appear on a map. We believe that the FSNS dataset is large and complex enough to train a deep network of significant complexity to solve the street name extraction problem "end-to-end" or to explore the design trade-offs between a single complex engineered network and multiple sub-networks designed and trained to solve sub-problems. We present such an "end-to-end" network/graph for Tensor Flow and its results on the FSNS dataset., Comment: Presented at the IWRR workshop at ECCV 2016