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This study delves into the thermoelectric properties of armchair black phosphorene nanoribbons while considering the presence of line edge roughness. Employing the tight‐binding method in conjunction with non‐equilibrium Green's function techniques and Landauer formulas, the impact of various parameters on thermoelectric performance is explored. These findings reveal that the electrical conductivity and, consequently, the power factor exhibits an increasing trend with expanding ribbon length and width. This behavior can be attributed to heightened collision rates, particularly in narrow ribbons, induced by line edge roughness as length increases. Remarkably, the Seebeck coefficient at the Fermi energy corresponding to the maximum power factor remains nearly constant across different widths, lengths, temperatures, and transport regimes. Furthermore, the thermoelectric figure of merit (ZT) demonstrates a positive correlation with both ribbon length and width. In narrow widths and lengths ≈1000 nm, the power factor and figure of merit exhibit an upward trend with ribbon width. However, with further increases in ribbon width, the influence of line edge roughness on thermal conductivity diminishes. Consequently, the figure of merit decreases due to the rise in thermal conductivity. Notably, the thermoelectric figure of merit is higher for short and narrow ribbons and long and wider ribbons. [ABSTRACT FROM AUTHOR]

An integrated automatic optical inspection (iAOI) system with a procedure was proposed for a printed circuit board (PCB) production line, in which pattern distortions and performance deviations appear with process variations. The iAOI system was demonstrated in a module comprising a camera and lens, showing improved supportiveness for commercially available hardware. The iAOI procedure was realized in a serial workflow of image registration, threshold setting, image gradient, marker alignment, and geometric transformation; furthermore, five operations with numerous functions were prepared for image processing. In addition to the system and procedure, a graphical user interface (GUI) that displays sequential image operation results with analyzed characteristics was established for simplicity. To demonstrate its effectiveness, self-complementary Archimedean spiral antenna (SCASA) samples fabricated via standard PCB fabrication and intentional pattern distortions were demonstrated. The results indicated that, compared with other existing methods, the proposed iAOI system and procedure provide unified and standard operations with efficiency, which result in scientific and unambiguous judgments on pattern quality. Furthermore, we showed that when an appropriate artificial intelligence model is ready, the electromagnetic characteristic projection for SCASAs can be simply obtained through the GUI. [ABSTRACT FROM AUTHOR]

The recent advances in super-resolution fluorescence microscopy, including single-molecule localization microscopy (SMLM), has enabled the study of previously inaccessible details, such as the organization of proteins within cellular compartments and even nanostructures in nonbiological nanomaterials, such as the polymers and semiconductors. With such developments, the need for the development of various computational nanostructure analysis methods for SMLM images is also increasing; however, this has been limited to protein cluster analysis. In this study, we developed an edge structure analysis method for pointillistic SMLM images based on the line edge roughness and power spectral density analyses. By investigating the effect of point properties in SMLM images, such as the size, density, and localization precision on the roughness measurement, we successfully demonstrated this analysis method for experimental SMLM images of actual samples, including the semiconductor line patterns, cytoskeletal elements, and cell membranes. This systematic investigation of the effect of each localization rendering parameter on edge roughness measurement provides a range for the optimal rendering parameters that preserve the relevant nanoscale structure of interest. These new methods are expected to expand our understanding of the targets by providing valuable insights into edge nanoscale structures that have not been previously obtained quantitatively.

The edge of a micro-/nanoscale line pattern fabricated by lithography is not a straight line as in the design but has a roughness. This is called the line edge roughness (LER) and is important dimensional information related to the device performance, and reference standards containing known LER values are needed for fundamental research on lithography-related technology. We propose a novel framework for developing LER reference standards that contain the necessary characteristics. The proposed framework has three main features: (i) a self-affine fractal roughness model for the development of next-generation devices; (ii) a reliable evaluation method based on LER reference metrology using SI-traceable atomic force microscopy (AFM); and (iii) a versatile evaluation method using scanning electron microscopy-based LER metrology verified by the previous AFM-based LER reference metrology. In an experiment to verify the proposed framework, we fabricated an LER reference standard by using electron-beam lithography. The results show that the proposed framework can be used to develop LER reference standards for next-generation functional micro-/nanostructures. • Developmental framework of line edge roughness reference standards. • Precise control and measurement of roughness profile based on a self-affine fractal. • This framework allows the evaluation of fabrication fidelity of the developed sample. [ABSTRACT FROM AUTHOR]

The high-volume manufacturing of the next generation of semiconductor devices requires state-of-the-art statistical analyses to reduce measurement uncertainties. Prediction intervals can characterize the reliability of the predictive performance of regression models. Normalized conformal prediction is a mathematically motivated approach to find distribution-free prediction intervals which depends on skillful modeling to evaluate a regression model fit to training data, and quantile regression is a classical and widely applied guideline to devise prediction intervals. Noise levels impact the reliability of line edge roughness estimates from noisy scanning electron microscope images. We propose procedures to generate prediction intervals based on image denoising and other image processing techniques and demonstrate significant improvements over earlier methods developed for the deep convolutional neural network EDGENet. [ABSTRACT FROM AUTHOR]

An integrated automatic optical inspection (iAOI) system with a procedure was proposed for a printed circuit board (PCB) production line, in which pattern distortions and performance deviations appear with process variations. The iAOI system was demonstrated in a module comprising a camera and lens, showing improved supportiveness for commercially available hardware. The iAOI procedure was realized in a serial workflow of image registration, threshold setting, image gradient, marker alignment, and geometric transformation; furthermore, five operations with numerous functions were prepared for image processing. In addition to the system and procedure, a graphical user interface (GUI) that displays sequential image operation results with analyzed characteristics was established for simplicity. To demonstrate its effectiveness, self-complementary Archimedean spiral antenna (SCASA) samples fabricated via standard PCB fabrication and intentional pattern distortions were demonstrated. The results indicated that, compared with other existing methods, the proposed iAOI system and procedure provide unified and standard operations with efficiency, which result in scientific and unambiguous judgments on pattern quality. Furthermore, we showed that when an appropriate artificial intelligence model is ready, the electromagnetic characteristic projection for SCASAs can be simply obtained through the GUI.

Enabling extreme ultraviolet lithography (EUVL) as a viable and efficient sub-10 nm patterning tool requires addressing the critical issue of reducing line edge roughness (LER). Stochastic effects from random and local variability in photon distribution and photochemical reactions have been considered the primary cause of LER. However, polymer chain conformation has recently attracted attention as an additional factor influencing LER, necessitating detailed computational studies with explicit chain representation and photon distribution to overcome the existing approach based on continuum models and random variables. We developed a coarse-grained molecular simulation model for an EUV patterning process to investigate the effect of chain conformation variation and stochastic effects via photon shot noise and acid diffusion on the roughness of the pattern. Our molecular simulation demonstrated that final LER is most sensitive to the variation in photon distributions, while material distributions and acid diffusion rate also impact LER; thus, the intrinsic limit of LER is expected even at extremely suppressed stochastic effects. Furthermore, we proposed and tested a novel approach to improve the roughness by controlling the initial polymer chain orientation. [ABSTRACT FROM AUTHOR]

Extensive numerical simulations of FinFET structures have been carried out using commercial TCAD tools. A series of plasma etching steps has been simulated for different process conditions in order to evaluate the influence of plasma pressure, composition and powering on the FinFET topography. Next, the most important geometric parameters of the FinFETs have been varied and the electrical characteristics have been calculated in order to evaluate the sensitivity of the FinFET electrical parameters on possible FinFET structure variability.

The impact of different variability sources on the transistor performance increases as devices are scaled-down, being the metal grain granularity (MGG) and the line edge roughness (LER) some of the major contributors to this increase. Variability studies require the simulation of large samples of different device configurations to have statistical significance, increasing the computational cost. A novel Pelgrom-based predictive (PBP) model that estimates the impact of MGG and LER through the study of the threshold voltage standard deviation $\left(\sigma V_{T h}\right)$ , is proposed. This technique is computationally efficient since once the threshold voltage mismatch is calculated, $\sigma V_{T h}$ can be predicted for different gate lengths $\left(L_{g}\right)$ , cross-sections, and intrinsic variability parameters, without further simulations. The validity of the PBP model is demonstrated for three state-of-the-art architectures (FinFETs, nanowire FETs, and nanosheet FETs) with different $L_{g}$ , cross-sections, and drain biases $\left(V_{D}\right)$ . The relative errors between the predicted and simulated data are lower than 10%, in the 92% of the cases.

Nanolithography with self‐assembled block copolymers (BCPs) is an emerging competitive alternative to conventional lithography, which is currently reaching its limits with regard to resolution and economic feasibility. For high‐resolution lithography, both the abruptness of BCP internal interfaces between self‐assembled polymer nanodomains and the processing steps used to selectively remove one of the polymers are crucial. This paper presents a detailed investigation of the chemistry, the mask wall morphology, and the line edge roughness (LER) of self‐assembled nanomasks from polystyrene‐b‐polymethylmethacrylate (PS‐b‐PMMA) before and after selective removal of the PMMA nanodomains. For the latter, either wet or plasma etching are employed and their impact on both the morphology and chemistry of resulting nanomasks is analysed using analytical (scanning) transmission electron microscopy (STEM), X‐ray photoelectron spectroscopy and polarization‐modulated infrared reflection‐absorption spectroscopy. Dedicated image analysis tools are developed to determine for the first time the LER of cylindrical openings in PS masks from STEM dark‐field images at sub‐nanometer resolution. Applying these tools prior to and after PMMA removal from the BCP films, the statistics of feature sizes, LERs, and interfacial widths are determined. In addition, the impact of wet and dry etching processes on PS‐co‐PMMA random copolymer brushes required for substrate functionalization is evaluated. [ABSTRACT FROM AUTHOR]

Line edge roughness (LER) has been an important issue in the nanofabrication research, especially in integrated circuits. Despite numerous research studies has made efforts on achieving smaller LER value, a strategy to achieve sub-nanometer level LER still remains challenging due to inability to deposit energy with a profile of sub-nanometer LER. In this work, we introduce a strategy to fabricate structures with sub-nanometer LER, specifically, we use scanning helium ion beam to expose hydrogen silsesquioxane (HSQ) resist on thin SiNx membrane (∼20 nm) and present the 0.16 nm spatial imaging resolution based on this suspended membrane geometric construction, which is characterized by scanning transmission electron microscope (STEM). The suspended membrane serves as an energy filter of helium ion beam and due to the elimination of backscattering induced secondary electrons, we can systematically study the factors that influences the LER of the fabricated nanostructures. Furthermore, we explore the parameters including step size, designed exposure linewidth (DEL), delivered dosage and resist thickness and choosing the high contrast developer, the process window allows to fabricate lines with 0.2 nm LER is determined. AFM measurement and simulation work further reveal that at specific beam step size and DEL, the nanostructures with minimum LER can only be fabricated at specific resist thickness and dosage., (© 2024 IOP Publishing Ltd. All rights, including for text and data mining, AI training, and similar technologies, are reserved.)

A drain current local variability compact model due to random fluctuation of channel length induced by line edge roughness/line width roughness (LER/LWR) is derived here. The random fluctuation of channel length leads to correlated fluctuations of threshold voltage and effective mobility of the current carriers. Therefore, an unified compact model is required to combine all the causes. Our model is based on the principle of propagation of variance. For the model verification purpose, calibrated technology computer aided design (TCAD) simulation platform is extensively used for all possible bias regions and several LER profile parameters. Channel profile optimization is critically studied with respect to different LER parameters, aiming reduction of ID variability. The model is further extended for SOI (Silicon-on-insulator) transistor and validated with literature data of threshold voltage and on-current variability. [ABSTRACT FROM AUTHOR]

Enabling extreme ultraviolet lithography (EUVL) as a viable and efficient sub-10 nm patterning tool requires addressing the critical issue of reducing line edge roughness (LER). Stochastic effects from random and local variability in photon distribution and photochemical reactions have been considered the primary cause of LER. However, polymer chain conformation has recently attracted attention as an additional factor influencing LER, necessitating detailed computational studies with explicit chain representation and photon distribution to overcome the existing approach based on continuum models and random variables. We developed a coarse-grained molecular simulation model for an EUV patterning process to investigate the effect of chain conformation variation and stochastic effects via photon shot noise and acid diffusion on the roughness of the pattern. Our molecular simulation demonstrated that final LER is most sensitive to the variation in photon distributions, while material distributions and acid diffusion rate also impact LER; thus, the intrinsic limit of LER is expected even at extremely suppressed stochastic effects. Furthermore, we proposed and tested a novel approach to improve the roughness by controlling the initial polymer chain orientation.

Methods for the generation and application of process variation-aware compact models for silicon photonics are presented. Three categories of process variations are considered. First, systematic variations, including die-to-die and spatial variations, are addressed with parameterized variation-aware compact models, and demonstrated for coupled resonator optical waveguide variation impact and yield analysis. Second, methods for random variation are presented, with ensemble and adjoint-based variation modeling methods. Third, particle defects are addressed with an extension to adjoint methods, enabling efficient analysis and identification of photonic component areas that are sensitive to defects. Finally, methods for extraction of variation models using variation test chip design and measurement are presented. Together, these methods are key components toward design-for-manufacturability approaches to achieve high yield and high performance in photonic integrated circuit design. [ABSTRACT FROM AUTHOR]

In this paper, variability analysis of a graded-channel dual-material (GCDM) double-gate (DG) strained-silicon (s-Si) MOSFET with fixed charges is analyzed using Sentaurus TCAD. By varying the different device parameters, the variability of the proposed GCDM-DG s-Si MOSFET is analyzed with respect to variations in threshold voltage, drain current, and short-channel effects as the line edge roughness and fluctuations in random dopant, contact resistance, and oxide thickness are considered. The results confirm that the effect of process variations is severe when the device has fixed charges at the oxide interface. Moreover, the proposed GCDM-DG s-Si p-MOSFET is less vulnerable to the effects of line edge roughness, fluctuations in oxide thickness, and random dopants in comparison with the proposed GCDM-DG s-Si n-MOSFET. Also, the proposed GCDM-DG s-Si MOSFET is more reliable when compared to the GC-DG s-Si MOSFET from the different variability sources. [ABSTRACT FROM AUTHOR]

Line-edge-roughness (LER) is one of undesirable process-induced random variation sources. LER is mostly occurred in the process of photo-lithography and etching, and it provokes random variation in performance of transistors such as metal oxide semiconductor field effect transistor (MOSFET), fin-shaped field effect transistor (FinFET), and gate-all-around field effect transistor (GAAFET). LER was analyzed/characterized with technology computer-aided design (TCAD), but it is fundamentally very time consuming. To tackle this issue, machine learning (ML)-based method is proposed in this work. LER parameters (i.e., amplitude, and correlation length X, Y) are provided as inputs. Then, artificial neural network (ANN) predicts 7-parameters [i.e., off-state leakage current (Ioff), saturation drain current (Idsat), linear drain current (Idlin), low drain current (Idlo), high drain current (Idhi), saturation threshold voltage (Vtsat), and linear threshold voltage (Vtlin)] which are usually used to evaluate the performance of FinFET. First, how datasets for training process of ANN were generated is explained. Next, the evaluation method for probabilistic problem is introduced. Finally, the architecture of ANN, training process and our new proposition is presented. It turned out that the prediction results (i.e., non-Gaussian distribution of device performance metrics) obtained from the ANN were very similar to that from TCAD in the respect of both qualitative and quantitative comparison.

Nanosheet field-effect transistors (NSFETs) have emerged as a novel device replacement for sub-7nm CMOS technology nodes. However, due to smaller fin thickness (Tfin = 5nm), NSFETs are more vulnerable to the process-induced variations. Among various types of process-induced variations, Line edge roughness (LER) is becoming a significant concern for multi-gate field-effect transistors (MugFETs) with smaller feature sizes. In this article, we have reported and compared the impact of LER on the electrical characteristics of NSFETs and nanowire field-effect transistors (NWFETs) for the sub-7nm technology node. We have generated a 3-D LER profile using 2-D Auto Covariance Function (ACVF) that considers two degrees of freedom for a realistic roughness analysis at advanced CMOS technology nodes. For a complete study of 3-D LER effect in NSFET, we have considered roughness along the nanosheet's sidewalls as well as top and bottom surfaces. We have shown using 3D TCAD simulations that the sidewall roughness in NSFETs contributes to a negligible mismatch in threshold voltage and ON current. The mismatch performance of NSFET is compared with that of the NWFET for sub-7nm technology node. NSFET appears to be more immune to mismatch in ON current than NWFETs considered in this work. On the other hand, as compared with NSFET, owing to its superior gate all-around control, the NWFET achieves lower mismatch in drain induced barrier lowering (DIBL) and subthreshold slope (SS) in presence of LER. In addition to this, FETs with different channel doping modes such as inversion (IM) and Junction less (JL) mode have been compared for their matching performance against 3-D LER. It can be concluded from the results that IM FETs are more immune to 3-D LER as compared to JL FETs.

ML (Machine Learning)-based artificial neural network (ANN) model is proposed to estimate the LER (line edge roughness)-induced performance variation in Fin-shaped Field Effect Transistor (FinFET). For a given LER features such as rms amplitude(Δ), correlation length along x-direction (AX), and correlation length along y-direction (AY), the metrics for device performance such as on-state drive current, off-state leakage current, threshold voltage, and subthreshold swing can be computing-efficiently estimated with the ANN model.

Quantitative analysis of line edge roughness (LER) is very important for understanding the root causes of LER and thereby improving the pattern quality in near-field lithography (NFL), because LER has become the main limiter of critical dimension (CD) control as the feature size of nanostructures is scaled down. To address this challenge, the photoresist point-spread function of NFL with a contact plasmonic ridge nanoaperture can be employed to account for the physical and chemical effects involved in the LER-generation mechanism. Our theoretical and experimental results show that the sources of LER in NFL mainly come from the aerial image, material chemistry, and process. Importantly, the complicated decay characteristics of surface plasmon waves are demonstrated to be the main optical contributor. Because the evanescent mode of surface plasmon polaritons (SPPs) and quasi-spherical waves (QSWs) decay in the lateral direction, they can induce a small image log-slope and low photoresist contrast, leading to a large LER. We introduce an analytical model and demonstrate the relationship between LER and CD to estimate the pattern quality in NFL. We expect that these results can provide alternative approaches to further improve pattern uniformity and resolution, which can lead to advanced nanopatterning results in NFL.

Variability of semiconductor devices is seriously limiting their performance at nanoscale. The impact of variability can be accurately and effectively predicted by computer-aided simulations in order to aid future device designs. Quantum corrected (QC) drift-diffusion (DD) simulations are usually employed to estimate the variability of state-of-the-art non-planar devices but require meticulous calibration. More accurate simulation methods, such as QC Monte Carlo (MC), are considered time consuming and elaborate. Therefore, we predict TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability on a 10-nm gate length gate-all-around Si nanowire FET and perform a rigorous comparison of the QC DD and MC results. In case of the MGG, we have found that the QC DD predicted variability can have a difference of up to 20% in comparison with the QC MC predicted one. In case of the LER, we demonstrate that the QC DD can overestimate the QC MC simulation produced variability by a significant error of up to 56%. This error between the simulation methods will vary with the root mean square (RMS) height and maximum source/drain $n$ -type doping. Our results indicate that the aforementioned QC DD simulation technique yields inaccurate results for the ON-current variability.

To reach its potential as an emerging technology platform, integrated silicon photonics needs accompanying design-for-manufacturability (DFM) methods and tools to assist the design of silicon photonic devices and circuits. Here, we explore spatial sampling in adjoint-based methods for analysis of the sensitivity of photonic components against key fabrication process variations. We apply and test these spatial sampling adjoint analysis methods to examine the impact of line edge roughness (LER) on a passive Y-branch at a given operating wavelength, achieving about 3% relative error. We extend the approach to also study LER variation sensitivity across a range of wavelengths and validate our results with ensemble virtual fabrication and FDTD simulations. The adjoint sensitivity and variance estimation of Y-branch transmission imbalance is seen to be highly efficient in comparison to direct ensemble simulation, with consistent results in the 95% confidence interval. [ABSTRACT FROM AUTHOR]

Scanning electron microscopy images are an attractive option to estimate the roughness of nanostructures. Convolutional neural network (CNN) based algorithms have improved scanning electron microscope (SEM) image denoising and estimation of line roughness measurements. However, these algorithms need improvements to run at high speeds with a low memory footprint and without compromising accuracy. We introduce two approaches to reduce computation time and memory. We first propose deep CNNs LineNet1 and LineNet2 to perform simultaneous denoising and edge estimation on rough line SEM images. This multiple task formulation in LineNet1 and LineNet2 reduces training time, inference time and model sizes. LineNet2 also facilitates edge estimation in the multiple-line images and generalizes the approach for other geometries. Our training method uses supervised learning datasets of single-line SEM images and multiple-line SEM images together with edge positions information. We next consider multiple visualization tools to improve our understanding of the LineNet1 architecture and use the resulting insights from these visualizations to motivate a study of two variations of LineNet1 with fewer neural network layers. One of these visualization techniques is new to the visualization of denoising CNNs. Our results show that these approaches significantly reduce the memory and computation needed for edge estimation with a slight impact on accuracy. [ABSTRACT FROM AUTHOR]

One of the main issues of EUV lithography is Line Edge Roughness (LER) on photo-resists, which significantly impacts yield at sub-30 nm pitches. In this work, an analytical model of LER is presented and analyzed for yield loss induced by open/short failures, cut mask defects, enhanced time dependent dielectrics breakdown (TDDB) failures for metal wires with different geometries, electro-migration (EM) impacts from the presence of LER on SRAM bitlines, and finally, LER impacts on functional errors. The model will be evaluated on single and double patterned designs with metal pitches of 24 and 28 nanometers. We show experimental results and give specific criteria in which LER thresholds can be relaxed without negatively impacting yield and path delay. This is a critical issue as higher LER tolerance allows exponential increase in throughput and thus reduces cost of fabrication. [ABSTRACT FROM AUTHOR]

Pitch uncertainty and line edge roughness are among the critical quality attributes of a pitch standard and normally the analyses of these two parameters are separate. The analysis of self-traceable Cr atom lithography nano-gratings shows a positive relevance and sensitivity between LER and evaluated standard deviation of pitch. Therefore, LER can be used as an aided pre-evaluation parameter for the pitch calculation method, such as the gravity center method or the zero-crossing points method. The optimization of the nano-grating evaluation method helps to obtain the accurate pitch value with fewer measurements and provide a comprehensive characterization of pitch standards.

Although several years delayed than its initial plan, extreme UV lithography (EUVL) with 13.5nm wavelength has been finally implemented into high volume manufacture (HVM) of mainstream semiconductor industry since 2018. With the delivery and installation of ASML EUV scanners in those giant Fab players like Samsung, TSMC and Intel, EUV lithography is becoming a sort of industry standard exposure metrology for those critical layers of advanced technology nodes beyond 7nm. Although ASML NXE EUVL scanner is the only commercialized EUV exposure system available on the market, its development is the concentration of all essence from worldwide industrial and academic collaboration. It is becoming more and more important not only for fab runners but also for main stream fabless design houses to understand and participate the progress of EUVL. In this review, working principles, module structures and technical challenges have been briefly discussed regarding each EUV subsystem, including light source, reflection mirrors and system, reticle module as well as photoresist development. EUV specific issues of light intensity, defectivity within reflection system, line edge roughness (LER) and mask 3D effects have been focused respectively and promising solutions have been summarized as well.

Background: Extreme ultraviolet (EUV) lithography was introduced for the high-volume manufacturing of state-of-the-art semiconductor devices in 2019. One of the issues for the CD metrology of an EUV resist pattern is resist shrinkage since the ratio of the shrinkage to the CD increases in EUV lithography compared with that in immersion argon fluoride lithography. Aim: A CD-SEM metrology for an EUV resist that was compatible with low shrinkage and high spatial resolution was investigated by using primary electrons (PEs) with high energy. Approach: The shrinkage, image sharpness, repeatability, and line edge roughness (LER) were evaluated the EUV resist using PEs with energies of 200, 800, and 4000 eV. Results: The smallest shrinkage was obtained under the conditions of the repeatability from 0.15 to 0.22 nm using PEs with an energy of 4000 eV. Moreover, the LERs obtained for 200, 800, and 4000 eV were almost same. Conclusions: While the electron irradiation damage for an under layer and the amount of shrinkage depend on pattern size could cause issues, the high voltage CD-SEM provides a solution to CD monitoring in high-volume manufacturing using EUV lithography. [ABSTRACT FROM AUTHOR]

We report a sub-30-nm pitch self-aligned double patterning (SADP) integration scheme with EUV lithography coupled with self-aligned block technology targeting the back end of line metal line patterning applications for logic nodes beyond 5 nm. The integration demonstration is a validation of the scalability of a previously reported flow, which used 193-nm immersion SADP targeting a 40-nm pitch with the same material sets (Si3N4 mandrel, SiO2 spacer, spin on carbon, spin on glass). The multicolor integration approach is successfully demonstrated and provides a valuablemethod to address overlay concerns and, more generally, edge placement error as a whole for advanced process nodes. Unbiased line edge roughness (LER)/line width roughness (LWR) analysis comparison between EUV SADP and 193-nm immersion SADP shows that both integrations follow the same trend throughout the process steps. While EUV SADP shows increased LER after mandrel pull, metal hardmask open, and dielectric etch compared to 193-nmimmersion SADP, the final process performance is matched in terms of LWR (1.08-nm 3 sigma unbiased) and is 6% higher than 193-nm immersion SADP for average unbiased LER. Using EUV, SADP enables almost doubling the line density while keeping most of the remaining processes and films unchanged and provides a compelling alternative to other multipatterning integrations, which present their own sets of challenges. [ABSTRACT FROM AUTHOR]

Two fundamental challenges of line edge roughness (LER) metrology are to provide complete and accurate measurement of LER. We focus on recent advances concerning both challenges inspired by mathematical and computational methods. Regarding the challenge of completeness: (a) we elaborate on the multifractal analysis of LER, which decomposes the scaling behavior of edge undulations into a spectrum of fractal dimensions similarly to what a power spectral density (PSD) does in the frequency domain. Emphasis is given on the physical meaning of the multifractal spectrum and its sensitivity to pattern transfer and etching; (b) we present metrics and methods for the quantification of cross-line (interfeature) correlations between the roughness of edges belonging to the same and nearby lines. We will apply these metrics to quantify the correlations in a self-aligned quadruple patterning lithography. Regarding the challenge of accuracy, we present a PSD-based method for a noise-reduced (sometimes called unbiased) LER metrology and validate it through the analysis of synthesized SEM images. Furthermore, the method is extended to the use of the height-height correlation functions to deliver noise-reduced estimation of the correlation length and the roughness exponent of LER. [ABSTRACT FROM AUTHOR]

Measurement of line edge roughness (LER) is discussed from four aspects: edge detection, power spectrum densities (PSD) prediction, sampling strategy, and noise mitigation. General guidelines and practical solutions for LER measurement today are introduced. Advanced edge detection algorithms such as the wavematching method are shown to be effective for robustly detecting edges from low SNR images, whereas a conventional algorithm with weak filtering is still effective in suppressing SEM noise and aliasing. An advanced PSD prediction method such as the multitaper method is effective in suppressing sampling noise within a line edge to analyze, whereas a number of lines are still required for suppressing line-to-line variation. Two types of SEM noise mitigation methods, such as the "apparent noise floor" subtraction method and LER-noise decomposition using regression analysis, are verified to successfully mitigate SEM noise from PSD curves. These results are extended to local critical-dimension uniformity (LCDU) measurement to clarify the impact of SEM noise and sampling noise on LCDU. [ABSTRACT FROM AUTHOR]

This paper introduces a new type of black photoresist with a very low reflectance and very smooth pattern line edge that doesn't require adding micron‐size particles. Combinations of poor solvent, good solvent, and selected special substances as solutes in the black photoresist can achieve matte surface during drying process. Because particles are not used to achieve matte surface, the line edge will be very smooth. This photoresist is likely appropriate for applications where light reflection or light scattering should be avoided, such as black matrix and smartphone camera surroundings. [ABSTRACT FROM AUTHOR]

With the evolution of sub-20 nm FinFET technology, line edge roughness (LER) has been identified as a critical problem and may result in critical device parameter variation and performance limitation in the future VLSI circuit application. In the present work, an analytical model of fin-LER has been presented, which shows the impact of correlated and uncorrelated LER on FinFET structure. Further, the influence of correlated and uncorrelated fin- LER on all electrical performance parameters is thoroughly investigated using the three-dimensional (3-D) Technology Computer Aided Design (TCAD) simulations for 14-nm technology node. Moreover, the impact of all possible fin shapes on threshold voltage ( V TH ), drain induced barrier lowering ( DIBL ), on-current ( I ON ), and off-current ( I OFF ) has been compared with the well calibrated rectangular FinFET structure. In addition, the influence of all possible fin geometries on the read stability of six-transistor (6-T) Static-Random-Access-Memory (SRAM) has been investigated. The study reveals that fin-LER plays a vital role as it directly governs the electrostatics of the FinFET structure. This has been found that there is a high degree of fluctuations in all performance parameters for uncorrelated fin-LER type FinFETs as compared to correlated fin-LER with respect to rectangular FinFET structure. This paper gives physical insight of FinFET design, especially in sub-20 nm technology nodes by concluding that the impact of LER on electrical parameters are minimum for correlated LER. [ABSTRACT FROM AUTHOR]

Analysis of physical modeling results can provide unique insights into extreme ultraviolet stochastic variation, which augment, and sometimes refute, conclusions based on physical intuition and even wafer experiments. Simulations verify the primacy of "imaging critical" counting statistics (photons, electrons, and net acids) and the image/blur-dependent dose sensitivity in describing the local edge or critical dimension variation. But the failure of simple counting when resist thickness is varied highlights a limitation of this exact analytical approach, so a calibratable empirical model offers useful simplicity and convenience. Results presented here show that a wide range of physical simulation results can be well matched by an empirical two-parameter model based on blurred image log-slope (ILS) for lines/spaces and normalized ILS for holes. These results are largely consistent with a wide range of published experimental results; however, there is some disagreement with the recently published dataset of De Bisschop. The present analysis suggests that the origin of this model failure is an unexpected blurred ILS:dose-sensitivity relationship failure in that resist process. It is shown that a photoresist mechanism based on high photodecomposable quencher loading and high quencher diffusivity can give rise to pitch-dependent blur, which may explain the discrepancy. [ABSTRACT FROM AUTHOR]

Pitch uncertainty and line edge roughness are among the critical quality attributes of a pitch standard and normally the analyses of these two parameters are separate. The analysis of self-traceable Cr atom lithography nano-gratings shows a positive relevance and sensitivity between LER and evaluated standard deviation of pitch. Therefore, LER can be used as an aided pre-evaluation parameter for the pitch calculation method, such as the gravity center method or the zero-crossing points method. The optimization of the nano-grating evaluation method helps to obtain the accurate pitch value with fewer measurements and provide a comprehensive characterization of pitch standards. [ABSTRACT FROM AUTHOR]

Lamellar gratings are widely used diffractive optical elements; gratings etched into Si can be used as structural elements or prototypes of structural elements in integrated electronic circuits. For the control of the lithographic manufacturing process, a rapid in-line characterization of nanostructures is indispensable. Numerous studies on the determination of regular geometry parameters of lamellar gratings from optical and extreme ultraviolet (EUV) scattering highlight the impact of roughness on the optical performance as well as on the reconstruction of these structures. Thus, a set of nine lamellar Si gratings with a well defined line edge roughness or line width roughness were designed. The investigation of these structures using EUV small-angle scattering reveals a strong correlation between the type of line roughness and the angular scattering distribution. These distinct scattering patterns open new paths for the unequivocal characterization of such structures by EUV scatterometry. [ABSTRACT FROM AUTHOR]

Using a state-of-the-art quantum transport simulator based on the effective mass approximation, we have thoroughly studied the impact of variability on Si x Ge 1 − x channel gate-all-around nanowire metal-oxide-semiconductor field-effect transistors (NWFETs) associated with random discrete dopants, line edge roughness, and metal gate granularity. Performance predictions of NWFETs with different cross-sectional shapes such as square, circle, and ellipse are also investigated. For each NWFETs, the effective masses have carefully been extracted from s p 3 d 5 s ∗ tight-binding band structures. In total, we have generated 7200 transistor samples and performed approximately 10,000 quantum transport simulations. Our statistical analysis reveals that metal gate granularity is dominant among the variability sources considered in this work. Assuming the parameters of the variability sources are the same, we have found that there is no significant difference of variability between SiGe and Si channel NWFETs.

In sub-20 nm CMOS technology nodes, the parameter variability has become a main hurdle during the scaling of devices. Recently, the use of metal gate stacks in nano-scale FinFET structure has a significant impact on the intrinsic parameter fluctuations due to the granular nature of metals. A 14 nm FinFET structure has been considered to study the impact of metal-gate work-function variability by using the 3-D device and mixed mode circuit simulation. The present work investigates the impact of work function variability (WFV) on electrical characteristics of various possible FinFET architectures followed by the regression model. Further, the investigation has been extended to study the stability performance of 6-T SRAM cell under the influence of WFV. It is observed that work function variation may result in considerable performance degradation in device as well as SRAM operation in nano domain. [ABSTRACT FROM AUTHOR]