317 results on '"Linten, Dimitri"'
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2. Extensive assessment of the charge-trapping kinetics in InGaAs MOS gate-stacks for the demonstration of improved BTI reliability
3. Electrostatic discharge robustness of amorphous indium-gallium-zinc-oxide thin-film transistors
4. Fault Attack Investigation on TaOx Resistive-RAM for Cyber Secure Application
5. Effects of Geometry and Cycling on the Radiation Response of Charge-Trapping NAND Memory Devices With SiON Tunneling Oxide
6. A Pragmatic Model to Predict Future Device Aging
7. Negative Bias-Temperature Instabilities and Low-Frequency Noise in Ge FinFETs
8. Impact of on- and off-chip protection on the transient-induced latch-up sensitivity of CMOS IC
9. Efficient Reliability Testing of Emerging Memory Technologies Using Multiple Radiation Sources
10. ESD nMOSFETs in Advanced Bulk FinFET Technology With Dual S/D Epitaxy
11. TID Effects in Highly Scaled Gate-All-Around Si Nanowire CMOS Transistors Irradiated to Ultrahigh Doses
12. Fault Attack Investigation on TaOx Resistive-RAM for Cyber Secure Application
13. Negative-Bias-Stress and Total-Ionizing-Dose Effects in Deeply Scaled Ge-GAA Nanowire pFETs
14. Total-Ionizing-Dose Effects on Polycrystalline-Si Channel Vertical-Charge-Trapping Nand Devices
15. Deep Understanding of Electron Beam Effects on 2D Layered Semiconducting Devices Under Bias Applications
16. LaSiOₓ- and Al₂O₃-Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration
17. Efficient Modeling of Charge Trapping at Cryogenic Temperatures—Part II: Experimental
18. Efficient Modeling of Charge Trapping at Cryogenic Temperatures—Part I: Theory
19. HBM and CDM ESD Performance of Advanced Silicon Photonic Components
20. Investigation of the Impact of Hot-Carrier-Induced Interface State Generation on Carrier Mobility in nMOSFET
21. Cyclic Thermal Effects on Devices of Two‐Dimensional Layered Semiconducting Materials
22. Impact of Interface Layer on Device Characteristics of Si:HfO2-Based FeFET’s
23. 3-D Full-Band Monte Carlo Simulation of Hot-Electron Energy Distributions in Gate-All-Around Si Nanowire MOSFETs
24. Total-Ionizing-Dose Response of Highly Scaled Gate-All-Around Si Nanowire CMOS Transistors
25. Single-Event-Induced Charge Collection in Ge-Channel pMOS FinFETs
26. Single-Event Transient Response of Vertical and Lateral Waveguide-Integrated Germanium Photodiodes
27. Physics-based device aging modelling framework for accurate circuit reliability assessment
28. Physical Modeling the Impact of Self-Heating on Hot-Carrier Degradation in pNWFETs
29. ESD on-wafer characterization: is TLP still the right measurement tool?
30. LaSiO x - and Al 2 O 3 -Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration.
31. Effects of Back-Gate Bias on the Mobility and Reliability of Junction-Less FDSOI Transistors for 3-D Sequential Integration
32. Characterization and optimization of sub-32-nm FinFET devices for ESD applications
33. Correlated Time-0 and Hot-Carrier Stress Induced FinFET Parameter Variabilities: Modeling Approach
34. The potential of FinFETs for analog and RF circuit applications
35. Planar bulk MOSFETs versus FinFETs: An analog/RF perspective
36. Perpendicular magnetic anisotropy of Co\Pt bilayers on ALD HfO2.
37. Technology Impact on the Low Frequency Noise of Si and Si/SiGe Superlattice Input-Output FinFETs
38. Impact of interface layer on charge trapping in Si:HfO2 based FeFET
39. On the impact of Gate field-plate length and barrier layer thickness on TDDB lifetime of GaN-on-Si MISHEMT devices for RF/5G/mm-Wave applications
40. Gate-source-drain architecture impact on DC and RF performance of sub-100-nm elevated source/drain NMOS transistors
41. Total-Ionizing-Dose Effects in InGaAs MOSFETs With High-k Gate Dielectrics and InP Substrates
42. RF/High-Speed I/O ESD Protection: Co-optimizing Strategy Between BEOL Capacitance and HBM Immunity in Advanced CMOS Process
43. Correlated Time-0 and Hot-Carrier Stress Induced FinFET Parameter Variabilities: Modeling Approach
44. Discussion on the Figures of Merit of Identified Traps Located in the Si Film: Surface Versus Volume Trap Densities
45. Relevance of fin dimensions and high-pressure anneals on hot-carrier degradation
46. A Compact Physics Analytical Model for Hot-Carrier Degradation
47. Understanding and empirical fitting the breakdown of MgO in end-of-line annealed MTJs
48. Total-Ionizing-Dose Effects on InGaAs FinFETs With Modified Gate-stack
49. Polarization Dependence of Pulsed Laser-Induced SEEs in SOI FinFETs
50. Total-Ionizing-Dose Effects and Low-Frequency Noise in 30-nm Gate-Length Bulk and SOI FinFETs With SiO2/HfO2Gate Dielectrics
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