115 results on '"Liscidini, Antonio"'
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2. 4.5 A Reconfigurable, Multi-Channel Quantized-Analog Transmitter with <-35dB EVM and <-51dBc ACLR in 22nm FDSOI
3. A 36 GHz Bandwidth, High Linear, Low Power, Driver Modulator, in 28 nm CMOS Technology Based on Quantized-Analog Signal Processing
4. Unconventional Receiver Architectures
5. Reconfigurable Multi-Band OFDM UWB Receivers: Circuits and System Considerations
6. A 2GHz voltage mode power scalable RF-Front-End with 2.5dB-NF and 0.5dBm-1dBCP
7. A Reconfigurable Power-Efficient Quantized Analog RF Front-End With Smart Calibration
8. Optimization of Quantized Analog Signal Processing Using Genetic Algorithms and μ-Law
9. SSCS Circuit Analysis and Design Contest: The Winners of the 2022 Edition [Society News]
10. A 2-D GRO Vernier time-to-digital converter with large input range and small latency
11. A 2.4-GHz 1.3-mW OQPSK RF Front-End TX Based on an Injection-Locked Power Amplifier
12. Editorial Welcome to the IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS)
13. Temperature Compensation of Crystal References in NB-IoT Modems
14. Unconventional Receiver Architectures
15. Temperature Compensation of Crystal References in NB-IoT Modems
16. A Reconfigurable Passive Switched-Capacitor TX RF Front End With −57 dB ACLR2
17. A Third-Order Integrated Passive Switched-Capacitor Filter Obtained With a Continuous-Time Design Approach
18. Thermodynamics limits in Oscillators and Phase Locked Loops
19. A Quantized Analog RF Front End
20. Quantized Analog RX Front-End for SAW-Less Applications
21. Low-Power QPSK Transmitter Based on an Injection-Locked Power Amplifier
22. A low-power sub-GHz RF receiver front-end with enhanced blocker tolerance
23. A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers
24. Filtering ADCs for wireless receivers: A survey
25. A 150-μW 3rd-order butterworth passive-switched-capacitor filter with 92 dB SFDR
26. A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOS
27. F4: Wireless low-power transceivers for local and wide-area networks
28. Introduction to the December Special Issue on the 2016 IEEE International Solid-State Circuits Conference
29. Class-C PA-VCO Cell for FSK and GFSK Transmitters
30. A Simplified Model for Passive-Switched-Capacitor Filters With Complex Poles
31. 20.9 A 1.92mW filtering transimpedance amplifier for RF current passive mixers
32. Sub-mW Current Re-Use Receiver Front-End for Wireless Sensor Network Applications
33. A current re-use PA-VCO cell for low-power BLE transmitters
34. Bluetooth low energy receiver system design
35. 13.6 A 600μW Bluetooth low-energy front-end receiver in 0.13μm CMOS technology
36. Fundamentals of Modern RF Wireless Receivers: A Short Tutorial
37. A Current-Mode, Low Out-of-Band Noise LTE Transmitter With a Class-A/B Power Mixer
38. An Intuitive Analysis of Phase Noise Fundamental Limits Suitable for Benchmarking LC Oscillators
39. A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers
40. Designing Analog IC at University of Pavia
41. SAW-Less Analog Front-End Receivers for TDD and FDD
42. A low out-of-band noise LTE transmitter with current-mode approach
43. Introduction to the Special Issue on the 38th European Solid-State Circuits Conference (ESSCIRC)
44. A 2-D GRO vernier time-to-digital converter with large input range and small latency
45. An Intuitive Current-Driven Passive Mixer Model Based on Switched-Capacitor Theory
46. A Dither-Less All Digital PLL for Cellular Transmitters
47. A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps
48. A 2G/3G Cellular Analog Baseband Based on a Filtering ADC
49. A 6.7-to-9.2GHz 55nm CMOS hybrid Class-B/Class-C cellular TX VCO
50. A 36mW/9mW power-scalable DCO in 55nm CMOS for GSM/WCDMA frequency synthesizers
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