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Titanium nitride (TiN) films have been used as gate electrode on metal-oxide-semiconductor (MOS) devices. TiN effective work function (EWF) values have been often reported as suitable for pMOS. For nMOS devices, a gate electrode with sufficient low EWF value with a similar robustness as TiN is a challenge. Thus, in this work, aluminum (Al) is incorporated into the TiN layer to reduce the EWF values, which allows the use of this electrode in nMOS devices. Titanium aluminum (TiAl), Al, and aluminum nitride (AlN) layers were introduced between the high-k (HfO2) dielectric and TiN electrode as Al diffusion sources. Pt/TiN (with Al diffusion) and Pt/TiN/TiAl/TiN structures were obtained and TiN EWF values were reduced of 0.37 eV and 1.09 eV, respectively. The study of TiN/AlN/HfO2/SiO2/Si/Al structures demonstrated that AlN layer can be used as an alternative film for TiN EWF tuning. A decrease of 0.26 eV and 0.45 eV on TiN EWF values were extracted from AlN/TiN stack and AlN/TiN laminate stack, respectively. AlN/TiN laminate structures have been shown to be more effective to reduce the TiN work function than just increasing the AlN thickness. [ABSTRACT FROM AUTHOR]

In this paper, we show the coexistence of the bipolar and unipolar resistive-switching modes in NiO cells realized using an optimized oxidation process of a Ni blanket layer used as the bottom electrode. The two switching modes can be activated independent of the cell switching history provided the appropriate programming conditions are applied. The bipolar and unipolar switching modes are discussed as driven by electrochemical- and thermal-based mechanisms, respectively. The switching versatility between these two modes is demonstrated both for large oxidized Ni films and for Ni films oxidized at the bottom of small dimension contact holes. The perspective of selecting the desired switching mode in a scaled device made in a small diameter single hole is highly attractive because the specific advantages of the two modes broaden the application scope of the cell and enable larger flexibility in terms of memory architecture. [ABSTRACT FROM AUTHOR]

The oxidation characteristics of TiAlN films integrated in the bottom electrode (BE) stack of three-dimensional SrBi2Ta2O9-based (SBT) ferroelectric capacitors are investigated in the range of 650–800 °C. The patterned TiAlN\Ir\IrO2\Pt BE is encapsulated by a thin ferroelectric SBT film deposited by metal organic chemical vapor deposition and then crystallized ex situ at temperatures higher than 650 °C in oxygen. During this annealing step the TiAlN film oxidizes from the lateral side of the patterned BE mesas. Compared to the vertical oxidation in blanket TiAlN layers, the lateral oxidation rate in our capped patterned films is much larger for similar oxidation conditions. This lateral oxidation of the TiAlN is strongly correlated with the in-film SBT stress that depends upon the deposition temperature and the thickness of the SBT film: the higher the tensile stress in the SBT, the larger the TiAlN oxidation length induced. From a kinetic study, the lateral oxygen diffusion was found to be a self-limited process with activation energy of about 2.2 eV and a preexponential factor D0 of 7×10-3 cm2/s. This factor, one to two orders of magnitude higher than the one obtained in blanket TiAlN layers, is indicative of interfacial diffusion. The mechanism of the increased lateral oxidation can be understood by the high tensile stress of the SBT film at the sidewall of the ferroelectric capacitors that tends to tear apart the Ir/TiAlN interface and causes enlarged interfacial oxygen diffusion. The limiting step of the oxidation mechanism is identified as oxygen diffusion in the Al-depleted/Ti-rich TiAlN layer that lies beyond the Al-rich film found at the very edge of the capacitors, whereas on blanket films the oxygen diffusion is limited in the Al-rich surface layer region. [ABSTRACT FROM AUTHOR]

Ferroelectric random access memory (FeRAM) is an attractive candidate technology for embedded nonvolatile memory, especially in applications where low power and high program speed are important. Market introduction of high-density FeRAM is, however, lagging behind standard complementary metal-oxide semiconductor (CMOS) because of the difficult integration technology. This paper discusses the major integration issues for high-density FeRAM, based on SrBi2Ta2O9 (strontium bismuth tantalate or SBT), in relation to the fabrication of our stacked cell structure. We have worked in the previous years on the development of SBT-FeRAM integration technology, based on a so-called pseudo-three-dimensional (3D) cell, with a capacitor that can be scaled from quasi two-dimensional towards a true three-dimensional capacitor where the sidewalls will importantly contribute to the signal. In the first phase of our integration development, we integrated our FeRAM cell in a 0.35 μm CMOS technology. In a second phase, then, possibility of scaling of our cell is demonstrated in 0.18 μm technology. The excellent electrical and reliability properties of the small integrated ferroelectric capacitors prove the feasibility of the technology, while the verification of the potential 3D effect confirms the basic scaling potential of our concept beyond that of the single-mask capacitor. The paper outlines the different material and technological challenges, and working solutions are demonstrated. While some issues are specific to our own cell, many are applicable to different stacked FeRAM cell concepts, or will become more general concerns when more developments are moving into 3D structures. [ABSTRACT FROM AUTHOR]

The difficult scaling of ferroelectric random access memories with the complementary metal-oxide semiconductor technology roadmap requires integration of three-dimensional (3D) ferroelectric capacitors (FeCAP’s). In this work the unusual electrical behavior of 3D FeCAP sidewalls was studied by comparing the electrical properties of two-dimensional and 3D integrated FeCAP structures. We evidenced composition variations of the SrBi2Ta2O9 (SBT) film in the sidewalls with marked bismuth segregation during metal-organic chemical-vapor deposition (MOCVD) of the SBT film. The segregation was reduced after decreasing the deposition temperature from 440 °C, whereby the Bi-rich phase in the sidewalls does not contribute to polarization, down to 405 °C, whereby sidewall SBT contributes to polarization. After further optimization of the MOCVD conditions at 405 °C, the segregation is minimized and the ferroelectric contribution of the sidewall SBT is almost the same as the contribution of the planar SBT. As a result, 3D FeCAP’s integrated up to metal interconnection exhibit a remnant polarization Pr∼7.5 μC/cm2. [ABSTRACT FROM AUTHOR]

Analysis of photodepopulation of electron traps in HfO2 films grown by atomic layer deposition is shown to provide the trap energy distribution across the entire oxide bandgap. The presence is revealed of two kinds of deep electron traps energetically distributed at around Et ≈2.0 eV and Et ≈3.0 eV below the oxide conduction band. Comparison of the trapped electron energy distributions in HfO2 layers prepared using different precursors or subjected to thermal treatment suggests that these centers are intrinsic in origin. However, the common assumption that these would implicate O vacancies cannot explain the charging behavior of HfO2, suggesting that alternative defect models should be considered. [ABSTRACT FROM AUTHOR]

This paper reports on the integration of MOCVD SBT based stacked ferroelectric capacitors in a 0.35 μm CMOS technology for embedded FeRAM, using a ferroelectric capacitor (FeCap) that is scalable to a 3D configuration. The electrical parameters of the CMOS devices with and without FeCap integration are presented. No significant shifts of the CMOS characteristics are noticed after FeCap integration. Also the effects of the CMOS processing on the FeCaps are discussed. There is no degradation of the hysteresis loops of the FeCaps throughout the CMOS back-end-of-line processing, which proves that the integrated encapsulation layer effectively prevents any hydrogen induced damage. Another key element in the successful integration of stacked ferroelectric devices is the conductive oxygen barrier, which protects the plugs from oxidation. A low contact resistance and a high yield are obtained on plug contacts covered by the oxygen barrier. Also damage free etching is a critical issue in FeRAM integration. Excellent results are presented for the etch process to form the contacts to the electrodes. [ABSTRACT FROM AUTHOR]

The incorporation of chemical species during annealing at the interface between the Ru gate electrode and the dielectric perturbs the electrostatic potential, thus affecting the effective work function of the metal. For both SiO2 and HfO2 gate dielectrics, O2 anneal at 550 °C leads to Ru oxidation (i.e., to RuOx formation) at the Ru/dielectric interface, resulting in a higher effective work function than that of metallic Ru. In turn, when RuOx is exposed to hydrogen, a work function reduction occurs, caused by either a reduction of RuOx into Ru or hydroxyl incorporation at the interface. [ABSTRACT FROM AUTHOR]