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Your search keyword '"Lo, Kuo-Hsuan"' showing total 11 results
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11 results on '"Lo, Kuo-Hsuan"'

5. Demonstration of a HV BCD technology with LV CMOS process

Author

Huang, Tsung-Yi, primary, Huang, Chien-Hao, additional, Huang, Chih-Fang, additional, Yang, Ching-Yao, additional, Yeh, Wang-Chi Vincent, additional, Chu, Huang-Ping, additional, Chiu, Chien-Wei, additional, Lo, Kuo-Hsuan, additional, Su, Hung-Der, additional, Liu, Jing-Meng, additional, and Gong, Jeng, additional

Published
2015
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6. 0.18um BCD technology with best-in-class LDMOS from 6 V to 45 V

Author

Huang, Tsung-Yi, primary, Liao, Wen-Yi, additional, Yang, Ching-Yao, additional, Huang, Chien-Hao, additional, Yeh, Wang-Chi Vincent, additional, Huang, Chih-Fang, additional, Lo, Kuo-Hsuan, additional, Chiu, Chien-Wei, additional, Kao, Tzu-Cheng, additional, Su, Hung-Der, additional, and Chang, Kuo-Cheng, additional

Published
2014
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7. Failure mechanism for input buffer under CDM test

Author

Kao, Tzu‐Cheng, primary, Hung, Chung‐Yu, additional, Lee, Jian‐Hsing, additional, Lien, Chen‐Hsin, additional, Chiu, Chien‐Wei, additional, Lo, Kuo‐Hsuan, additional, Su, Hung‐Der, additional, and Weng, Wu‐Te, additional

Published
2014
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10. Using LV process to design high voltage DDDMOSFET and LDMOSFET with 3-D profile structure.

Author

Huang, Chien-Hao, Huang, Tsung-Yi, Yang, Ching-Yao, Chu, Huang-Ping, Lo, Kuo-Hsuan, Hung, Chung-Yu, Chang, Kuo-Cheng, Su, Hung-Der, Huang, Chih-Fang, and Gong, Jeng

Abstract

In this work, layout skills using three dimensional (3D) fish bone, slot, and island patterns to enhance the breakdown voltage of PW/NW junction of lateral MOSFETs is developed. Novel lateral double diffused MOSFETs (LDMOSFET) and Double Diffused Drain MOSFETs (DDDMOSFET) without any high voltage (HV) layer are achieved in a standard 5V low voltage (LV) CMOS technology. From the experiment results, the developed DDDMOSFETs and LDMOSFETs can be used for 10V and 60V application respectively. [ABSTRACT FROM PUBLISHER]

Published
2013
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11. Improving the Electrostatic Discharge Robustness of a Junction Barrier Schottky Diode Using an Embedded p-n-p BJT.

Author

Hung, Chung-Yu, Kao, Tzu-Cheng, Lee, Jian-Hsing, Gong, Jeng, Lo, Kuo-Hsuan, Su, Hung-Der, and Haung, Chih-Fang

Subjects
SCHOTTKY barrier diodes, ELECTROSTATICS, ELECTRIC discharges, SCHOTTKY barrier, SEMICONDUCTOR-metal boundaries
Abstract

The high-voltage (H-V) junction barrier Schottky (JBS) diode is often incorporated into the input or output of H-V integrated circuits. When the chip is connected to the external environment, it inevitably suffers electrostatic discharge (ESD) stress. However, the JBS diode can only withstand the forward-mode ESD but it is highly vulnerable to reverse-mode ESD. In this letter, a new kind of JBS diode that is incorporated with a p-n-p bipolar is developed. The experimental results demonstrated that the new device can improve the failure threshold voltages of the human body mode and machine mode by at least four times. The area increase for the new device is 2.2%. [ABSTRACT FROM AUTHOR]

Published
2014
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