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High-k oxide dielectric films are indispensable for low-power-consumption oxide thin-film transistors (TFTs) applied in advanced and portable electronics. However, high-quality oxide dielectric films prepared by solution process typically require sophisticated processes and long thermal annealing time, severely limiting both the throughput manufacturing and cost-effectiveness. In this study, the influence of different heating-up methods on the surface morphology and dielectric properties was systematically investigated. Gradient heating-up method could not only substantially improve the surface morphology and quality of high-k ZrO2 films but also efficiently shorten the annealing time. The gradient heating-up process was further designed on the basis of thermal behavior of the xerogel-like precursor, which successfully realize the preparation of high-quality ZrO2 films with an annealing time of 5 min (i.e. the efficiency of thermal treatment increased by about 89%). The ZrO2 film presented excellent dielectric properties, including a low leakage current density of ∼10−8 A cm−2 (at 2 MV cm−1), a large areal capacitance of 169 nF cm−2 and a high dielectric constant of 20.41 (1 MHz). Furthermore, InSnZnO TFT based on the ZrO2 gate dielectrics shows an acceptable device performances, such as a high carrier mobility of 2.82 cm2 V−1 s, a high on/off current ratio of ∼105 and a low subthreshold swing of 0.19 V decade −1 at a low operation voltage of 5 V. This work provide a highly promising approach to fabricate high-quality solution-processed high-k oxide dielectric films employed for large-scale and low-power-consumption electronics. [ABSTRACT FROM AUTHOR]

A novel Gm-C structure of a second-order continuous-time filter is proposed that allows for the independent control of the filter's natural frequency (ω0) and quality factor (Q). The structure consists of two capacitors and four transconductors. Two transconductors together with the capacitors form a lossless second-order circuit with tunable ω0. The other two transconductors form a variable gain amplifier (VGA) which realizes an adjustable loss and thereby adjustable Q. The proposed solution can be used to implement low-voltage and low-power tunable front-end filter banks for fully integrated CMOS cochlear implants and edge intelligence accelerators. An example filter bank powered by 0.5 V and consuming 40 nW of power per single filter is designed and simulated using a 180 nm CMOS process. Circuitries for the adaptive control of transistor bias at a reduced supply voltage are proposed. The ω0 and Q control circuitries are also proposed: a delay-locked loop (DLL)-based system for fine ω0 tuning and a binary-weighted current mirror for Q adjustment. The proposed solution allows for the independent regulation of ω0 and Q within the ranges of 0.25–8 kHz and 1–14, respectively, with a relative tolerance of up to 5% across a filter bank. [ABSTRACT FROM AUTHOR]

This paper proposes a low-power charge pump PLL (CPPLL) with 1-V supply voltage in 180-nm CMOS technology, which serves as a low-cost clock generator for heterogeneous integration. Tradeoffs between power consumption, jitter performance and limited loop bandwidth in the conventional CPPLL have been analyzed first, followed by the explanations on reference spur issues in wide bandwidth architectures. A novel two-stage ring oscillator with low voltage capability and linear control gain has been proposed and analyzed in detail, which facilitates the implementation of this 1-V design. Fabricated in SMIC 180-nm technology, the designed PLL occupies a die area of 0.177mm2 with an integrated loop filter. The PLL draws 1.8mA when working at 480MHz, and shows a rms jitter of 7.2pS, which is 20 times more power efficient compared with PLLs with similar frequency and technology node. The design shows potential for heterogeneous integration. [ABSTRACT FROM AUTHOR]

A novel highly π-extended heteroarene Benzo[1,2-b:4,5-b']di(naphtho[1,2-d]thiophene) (DBTBT) was used for organic field-effect transistors (OFETs). The mobilities of OFET were greatly improved from 0.34–0.58 cm2V−1s−1 to 1.02–1.75 cm2V−1s−1 by morphology tuning through 2 steps' controlling substrate temperature. More importantly, the OFETs showed a good ambient stability in 30 days measurements. The flexible OFET arrays were prepared on polyethylene terephthalate substrate with octadecyl trichlorosilane modified polymethylsilsesquioxane/polyacrylonitrile gate dielectrics and demonstrated a 100% yield. Further, this flexible cell was used for ultraviolet light detection, which showed good ability of detecting low power light (such as λ = 254 nm, 7 μW/cm2). [ABSTRACT FROM AUTHOR]

With the reduction of CMOS technology to nanometric dimensions, it is thought that the end of atomic limits in integrated circuit applications is almost approached and some problems are encountered in production. Carbon nanotube field effect transistors (CNTFETs) are considered a proper option to replace CMOS near term owing to their superior properties such as scalability and better channel electrostatics. For this purpose, a low-voltage, low-power Voltage Differencing Inverting Buffered Amplifier (VDIBA) structure is propose with a 32 nm CNTFET, in this article. The proposed CNTFET VDIBA structure operates with a bias current of 1 µA and consumes 14.32 µW of power with a supply voltage of ± 0.3 V. Compared to the traditional CMOS VDIBA structure, the power consumption is reduced by 733 times. Besides, proposed VDIBA structure has a bandwidth of 43.788 GHz. [ABSTRACT FROM AUTHOR]

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Oxygen evolution reaction at the anode consumes about 60–70% of the total power for the solid oxide electrolysis cell (SOEC), and power consumption can be greatly reduced by introducing hydrocarbon fuels such as methane into the anode for the oxidation reaction. In this work, rare-earth doped CeO 2 is used as catalyst support and oxygen ion conductor with Ni serving as an active metal for methane oxidation at the SOEC anode. The catalyst is synthesized via stepwise hydrolysis and impregnation methods, and the influences of rare-earth oxides on the performance of CH 4 thermal oxidation, SOEC anode oxidation and hydrogen production are studied. The results show that 5%Ni–Ce 0.8 Gd 0.2 O 2-δ exhibits the optimal catalytic oxidation and electrolytic hydrogen production with the lowest cell voltage of 0.38 V at 0.4 A/cm2. The high performance is mainly attributed to the oxygen vacancy, oxygen ion conductivity, and active metal dispersion. It is supposed that oxygen evolution reaction and simultaneous methane oxidation with generated oxygen occur at the SOEC anode can reduce oxygen partial pressure, which results in the ultra-low voltage for hydrogen production. [Display omitted] • Optimized oxygen vacancy and oxygen ion conductivity of rare-earth doped CeO 2 enhance the electrochemical oxidation. • The SOEC anode of Gd-doped CeO 2 realizes an ultra-low voltage of 0.38 V at 0.4 A/cm2. • OER and subsequently CH 4 oxidation is proposed for anode reactions to reduce operation voltage. [ABSTRACT FROM AUTHOR]

With approaching the limit value, many problems have arisen in the scaling of MOSFET sizes. Alternative solutions have been investigated for many problems such as short channel effects and reduced gate control, which are caused by reducing the size of the MOSFET. Carbon Nanotube Field Effect Transistor (CNTFET) is considered as the most suitable alternative to replace MOSFET with its superior electrical and mechanical properties. In this study, simulation studies of Voltage Differencing Gain Amplifier structure were carried out using 32 nm CNTFET. In addition, a three-input single-output filter structure is presented with the CNTFET VDGA structure. The filter structure realized at ±0.3V low supply voltage and 1µA low bias current has a higher center frequency of 22.909 MHz compared to the filter structure realized with CMOS VDGA. In addition, the filter made with CNTFET VDGA structure has a low power consumption of 8.3412 µW. [ABSTRACT FROM AUTHOR]

Redundant power supplies are commonly used in systems that require long-term uninterrupted operation and high reliability. When redundant power supplies are used as N+1 backup power supplies to supply power to devices at the same time, parallel current sharing must be considered.In order to solve the problem of large loss of passive redundant power supply and inability to achieve current equalization, this study adopts the design scheme of active redundancy and designs a 1+1 redundant power supply system with two parallel DC voltage inputs.The system uses GD32E103 as the main control chip. By changing the on-resistance of MOSFET(Metal-Oxide Semiconductor Field Effect Transistor), PI(Proportional Integral) control is adopted to realize the automatic balance of the output current of two redundant power supplies.The simulation and experimental results show that the active redundancy design scheme can achieve the purpose of automatic current equalization.In normal operation, the maximum error of the two current channels is less than 0.1 A, and the accuracy of current sharing meets the design requirements. [ABSTRACT FROM AUTHOR]

In-situ XRD, 31P NMR and 23Na NMR were used to analyze the interaction behavior of Na3V2(PO4)3 at low voltage, and then a new intercalation model was proposed. During the transition from Na3V2(PO4)3 to Na4V2(PO4)3, Na ions insert into M1, M2 and M3 sites simultaneously. Afterwards, during the transition of Na4V2(PO4)3 to Na5V2(PO4)3, Na ions mainly insert into M3 site. [ABSTRACT FROM AUTHOR]

Background: Cerebral computed tomography angiography (CTA) has revolutionized the diagnosis of neurovascular emergencies. Strategies to reduce radiation, a concern for cancer, involve tube voltage and current reduction but with increased noise and inferior image quality. Hence, the objective of the study was to evaluate the quality of images obtained through low-dose radiation and low-contrast volume CTA with an iterative reconstruction (IR) technique versus standard CTA without IR. Methods: This prospective trial involved 100 adults requiring cerebral CTA for cerebrovascular diseases. They were split into two groups: one with 120 kVp tube voltage and 80 mL contrast using filtered back projection, and the other with 80 kVp and 30 mL contrast with IR. Evaluation criteria included attenuation values, signal-to-noise ratio, contrast-to-noise ratio, and subjective assessments. Results: Compared to 120 kVp, 80 kVp showed higher vessel attenuation in the internal (272.91 ± 30.59 vs 405.52 ± 53.08; p <.001) and middle cerebral artery (247.55 ± 29.84 vs 372.55 ± 49.02; p <.001) regions. Brain parenchymal attenuation at the centrum semiovale was lower with 80 kVp (29.12 ± 1.87 vs 24.78 ± 2.94; p <.001), accompanied by higher noise. Signal-to-noise ratio (p <.001) and contrast-to-noise ratio (p <.05) were lower at 80 kVp. Image quality didn't significantly differ, and radiation exposure reduced significantly by 70% in the 80 kVp group, suggesting its diagnostic feasibility. Conclusions: The 80 kVp protocol for CTA of the cerebral vessels combined with lower contrast volume produces images with similar image quality with significant radiation effective dose and total iodine dose reduction. The 80 kVp protocol holds significant promise for replacing the standard 120 kVp protocol in cerebral CTA. [ABSTRACT FROM AUTHOR]

This paper introduces and experimentally validates a switched-capacitor inverter-based second-order 3-tap FIR single-bit Delta-Sigma Modulator ( $\Delta \Sigma $ M) designed for nanowatt-level analog-to-digital conversion in wearable healthcare devices. The focus is on applications with energy harvesters, emphasizing continuous monitoring of chronic conditions and closed-loop drug-delivery systems. The design methodology addresses ultralow-power considerations at both architectural and transistor levels, tackling challenges like process variations without relying on complex digital calibration techniques. Experimental results from prototypes, implemented on a standard 180-nm CMOS process, reveal a peak SINAD of 77.8 dB and SNR of 79.4 dB, with a power consumption of 71.5 nW at a 900-mV supply. Measurements across nine chip samples are consistent, demonstrating low DC offset, with low temperature drift and live sensitivity. The outcomes confirm the modulator suitability for energy-harvested wearable systems.

In the electrostatic precipitation of microparticles, it is common to evaluate the voltages between the corona onset voltage and the breakdown point. However, the charging of particles in the nanoscale size range mainly occurs by diffusion, suggesting the possibility of its occurrence, even at low values. This paper investigates the implications of a wide range of electric fields applied in the collection of nanoparticles (6.15–241.4 nm). Two electrostatic precipitators (P.I. and P.II.), both with plates 10 cm high and 30 cm long, but with different plate spacings (4 and 6.5 cm), were tested using three air velocities (1.9, 2.9, and 3.9 cm/s) and 36 electric fields (0.0 − 5.0 kV/cm). Under the highest electric fields, both precipitators showed efficiencies above 99.9%. Furthermore, nanoparticles were collected before the corona onset voltage, with efficiencies of around 28% (P.I.) and 35% (P.II.). Even though no current was detected by the high voltage source, charges on the particles were measured in electric fields lower than 3.0 kV/cm. The higher the applied voltage, the higher the residual charge of the particles at the precipitator outlet. It is expected that the findings of this work should contribute to the technological development of electrostatic processes for air treatment. [ABSTRACT FROM AUTHOR]

A novel floating gate MOS (FGMOS) low voltage-low power wide range fully differential difference current conveyor (FDDCCII) is proposed. Proposed FDDCCII has a power consumption of 375nW and a rail-to-rail input signal range. Appropriate selection of the ratio between total capacitance vs. input capacitance of FGMOS transistors leads to a decrease in the transconductance and this feature increases the input signal oscillation range of the FDDCCII. Some of the key properties of the proposed FDDCCII are the bandwidth of 31 Mhz and 26 MHz at current conveying curve and voltage conveying curve, respectively. [ABSTRACT FROM AUTHOR]

A CMOS realisation of a voltage tunable biquad filter using only MOSFET-based operational transconductance amplifier (OTA) and capacitors has been designed using silicon-based CMOS technology. It operates at a low supply voltage of $$0.25$$ 0.25 V at a $$500$$ 500 MHz frequency. The filter is theoretically analysed and then simulated using commercially available Cadence Virtuoso tools at $$0.18$$ 0.18 $$\mu m$$ μm CMOS technology parameters. The proposed design is used to implement second-order low pass, highpass, bandpass, and bandreject filters with the same circuit simply by tuning the input voltage. The bandwidth and cut-off frequency also can be changed by changing the capacitor values. [ABSTRACT FROM AUTHOR]

A novel low-power MOS-only voltage reference is presented. The Enz–Krummenacher–Vittoz (EKV) model is adopted to provide a new perspective on the operating principle. The normalized charge density, introduced as a new variable, serves as an indicator when trimming the output temperature coefficient. The proposed voltage reference consists of a specific current generator and a 5-bit trimmable load. Thanks to the good match between the current source stage and the output stage, the nonlinear temperature dependence of carrier mobility is automatically canceled out. The circuit is designed using 55 nm COMS technology. The operating temperature ranges from −40 ° C to 120 ° C. The average temperature coefficient of the output voltage can be reduced to 21.7 ppm/ ° C by trimming. The power consumption is only 23.2 nW with a supply voltage of 0.8 V. The line sensitivity and the power supply rejection ratio at 100 Hz are 0.011 %/V and −89 dB, respectively. [ABSTRACT FROM AUTHOR]

Low voltage oxide thin-film transistors (TFTs) operating below 1.0 V were developed using a high dielectric constant tantalum oxide produced by thermal oxidation. Thermal oxidation was carried out at 400, 500 and 600 °C under an oxygen atmosphere. The tantalum oxide was evaluated by X-ray photoelectron spectroscopy (XPS). XPS confirmed the binding energy of Ta4f, indicating the binding state of tantalum oxide. The bottom gate oxide TFT with the gate insulator of tantalum oxide grown at 500 °C exhibited mobility of 26.7 cm2/V s and a threshold voltage of 1.3 V. The transfer characteristics at the drain voltages below 1.0 V show its applicability to low voltage operation below 1 V. The bootstrapped inverter with developed oxide TFTs operated well at the 1.0 and 2.0 V operation voltages. [ABSTRACT FROM AUTHOR]

The decarburization of heat and transport using electric vehicles (EVs) and heat pumps (HPs) needs an important investment in low-voltage (LV) networks. This article proposes an optimization approach to estimate the availability of headroom for domestic EV charging and optimization on LV networks under various penetrations of heat pumps. The proposed optimization approach is called dynamic differential annealed optimization (DDAO). The objective of the proposed approach is to maximize the hosting capability of low-voltage networks for EVs and HPs by optimizing the flexibility of EV charging. The DDAO is used to optimize different aspects of EV charging and LV networks. The DDAO approach is implemented in three steps: (a) HP headroom assessment, (b) EV optimization, and (c) validation. The performance of the proposed method is validated on a MATLAB platform and compared with the existing Binary Spring Search Algorithm (BSSA), Manta Ray Foraging Optimization Algorithm (MRFO), and Chaos Game Optimization methods. In comparison to the total prices of 3.5£ in BSSA, 4.5£ in MRFO, and 5.5£ in CGO, the proposed DDAO method achieves a lower total price of 3.2£. This suggests that the DDAO method is more cost-effective than the existing techniques. [ABSTRACT FROM AUTHOR]

A DC microgrid is an efficient way to combine diverse sources; conventional droop control is unable to achieve both accurate current sharing and required voltage regulation. This paper provides a new adaptive control approach for DC microgrid applications that satisfies both accurate current sharing and appropriate voltage regulation depending on the loading state. As the load increases in parallel, so do the output currents of the distributed generating units, and correct current sharing is necessary under severe load conditions. The suggested control approach raises the equivalent droop gains as the load level increases in parallel and provides accurate current sharing. The droop parameters were checked online and changed using the principal current sharing loops to reduce the variation in load current sharing, and the second loop also transferred the droop lines to eliminate DC microgrid bus voltage fluctuation in the adaptive droop controller, which is different and inventive. The proposed algorithm is tested using a variety of input voltages and load resistances. This work assesses the performance and stability of the suggested method using a linearized model and verifies the results using an acceptable model created in MATLAB/SIMULINK Software Version 9.3 and using Real-Time Simulation Fundamentals and hardware-based experimentation. [ABSTRACT FROM AUTHOR]

The Emerging biomedical applications such as electrocardiography, electroencephalogram, wireless implantable devices have required optimized power-based SAR ADC in them to reduce package cost and to extend battery life. In view of power optimized SAR ADC, a dynamic controlled comparator with novel static power reduction logic incorporated with common mode kickback noise reduction technique is designed at 45 nm technology in CADENCE Virtuoso in this paper. Designed comparator is analyzed in terms of performance parameters; static power dissipation, transient power dissipation, maximum sampling rate, offset voltage and delay. Simulation and behaviour modeling analyses of proposed dynamic comparator has resulted in five times reduction in static power dissipation along with optimization of transient power and sampling rate as well compared to previously available double tail dynamic comparator. Moreover, it has been mentioned that proposed dynamic comparator is dissipating 2.36 pW of static power and 3.59 nW of transient power with sampling rate of 240 KS/s at 0.5 V. Further, the kickback noise of proposed design is limited to 4.7 mV with maximum delay of 124 ps. Finally, the novel outcomes of proposed comparator are the optimization in required parameters such as power, delay, offset voltage and kickback noise for biomedical applications as compared to double tail dynamic comparator. The proposed consideration for SAR ADC can become a backbone for low power biomedical applications. [ABSTRACT FROM AUTHOR]

In-situ XRD, 31P NMR and 23Na NMR were used to analyze the interaction behavior of Na3V2(PO4)3 at low voltage, and then a new intercalation model was proposed. During the transition from Na3V2(PO4)3 to Na4V2(PO4)3, Na ions insert into M1, M2 and M3 sites simultaneously. Afterwards, during the transition of Na4V2(PO4)3 to Na5V2(PO4)3, Na ions mainly insert into M3 site.

The global PV market has grown extensively for small- to large-scale systems. Inevitably, this leads to the increased development of PV technology. PV systems are intrinsically exposed to weather phenomena. One such phenomenon is lightning. Direct and indirect effects of lightning can cause damage to PV systems. However, lightning protection for PV systems is often neglected and existing standards for protection are underdeveloped. In this paper, previous work is analysed to understand the interaction between lightning and PV systems and to ascertain gaps in current knowledge thereof. Investigation of these aspects will ultimately assist in understanding lightning risk, protection system design and aid in the development of lightning protection standards for PV in the renewable energy industry. The article also presents a specific case study, outlining the lightning protection system of a 3200W photovoltaic plant on a farm. The work includes a thorough description of the lightning protection system, addresses issues related to the contamination of PV surfaces, and proposes practical measures to ensure the safe and reliable operation of photovoltaic systems under adverse weather conditions. The experimental results affirm the significance of implementing lightning protection systems to ensure the robust performance of solar power plants.

Vietnam has developed solar power very quickly in recent years. However, the integration of the solar power system into a distribution power grid can cause a clear effect on the voltage of the grid. Accordingly, the voltage at the nodes increases significantly because of the appearance of photovoltaic (PV) systems, and it can lead to overvoltage at some load nodes near the solar power source. The impact of solar power stations with distribution power grids depends on the location and operating conditions of the utility grid. Therefore, the study of the impact of rooftop solar power on the distribution grid needs to add actual operating data of the utility grid to achieve a more detailed assessment and reliability. This study analyzed the influence of rooftop solar power on a low voltage distribution power grid in Ha Tinh province, Vietnam with the support of ETAP software. The scenario was calculated for 50% of the power (3-phase) penetration gain of the transformer. Besides, a proposed synthetic solution is a combination of reactive power compensation with a 5kVAr minimum compensation level at many points on the grid and adjustment of the load tap at the appropriate level depending on the load situation of the transformer. Thus, the voltage of the nodes on the power grid is improved, and the power loss is also decreased.

This paper presents a low-voltage low-power chopper-stabilized differential difference amplifier (DDA) realized using 40 nm CMOS technology. Operating with a supply voltage of 0.5 V, a three-stage DDA has been employed to achieve an open-loop gain of 89 dB, while consuming just 0.74 μW of power. The proposed DDA incorporates feed-forward frequency compensation and a Type II compensator to achieve pole-zero cancellation and damping factor control. The DDA has a unity-gain bandwidth (UGB) of 170 kHz, a phase margin (PM) of 63.98°, and a common-mode rejection ratio (CMRR) of up to 100 dB. This circuit can effectively drive a 50 pF capacitor in parallel with a 300 kΩ resistor. The use of the chopper stabilization technique effectively mitigates the offset and 1/f noise. The chopping frequency of the chopper modulator is 5 kHz. The input noise is 245 nV/sqrt (Hz) at 1 kHz, and the input-referred offset under Monte Carlo cases is only 0.26 mV. Such a low-voltage chopper-stabilized DDA will be very useful for analog signal processing applications. Compared to the reported chopper DDA counterparts, the proposed DDA is regarded as that with one of the lowest supply voltages. The proposed DDA has demonstrated its effectiveness in tradeoff design when dealing with multiple parameters pertaining to power consumption, noise, and bandwidth. [ABSTRACT FROM AUTHOR]

This paper presents a novel current-mode true RMS–DC converter based on the dynamic translinear principle. The converter is designed using a third-order translinear loop, resulting in a very compact and simple circuit. The proposed circuit is designed in 65 nm CMOS technology, operates with 1 V power supply, has only 14 transistors and performs satisfactorily over a wide input current range of 300 nA–950 nA and for a frequency range of 600 Hz–650 kHz for a capacitance value of 10 nF. The frequency range of operation can be tuned by varying the external off chip capacitor and the bias current. The circuit consumes 20 nW static power, 1.6 μW maximum dynamic power and offers the lowest FOM among the other RMS–DC converter circuits presented in the literature. Comprehensive mathematical analysis along with the post layout simulation results confirm the validity of the proposed circuit. To test the use of converter in real world scenarios, the proposed converter is introduced within a typical ECG detection system and the results show that the circuit is an attractive solution for RMS–DC conversion in low-voltage low-power applications. [ABSTRACT FROM AUTHOR]

Growth in renewable energy systems, direct current (DC) microgrids, and the adoption of electric vehicles (EVs) will substantially increase the demand for bi-directional converters. Precise control mechanisms are essential to ensure optimal performance and better efficiency of these converters. This paper proposes a deep neural network (DNN)-based controller designed to precisely control bi-directional converters for vehicle-to-vehicle (V2V) and vehicle-to-grid (V2G) applications. This control technique allows the converter to quickly attain new reference values, enhancing performance and efficiency by significantly reducing the overshoot duration. To train the DNN controller, large synthetic data are used by performing simulations for various sets of conditions, and the results are validated with a hardware setup. The real-time performance of the DNN controller is compared with a conventional proportional–integral (PI)-based controller through simulated results using MATLAB Simulink (version 2023a) and with a real-time setup. The converter attains a new reference of about 975 μ s with the proposed control technique. In contrast, the PI controller takes about 220 ms, which shows that the proposed control technique is far better than the PI controller. [ABSTRACT FROM AUTHOR]

This paper investigates an adaptive body biasing (ABB) circuit to improve the reliability and variability of a low-voltage inductor–capacitor (LC) voltage-controlled oscillator (VCO). The ABB circuit provides VCO resilience to process variability and reliability variation through the threshold voltage adjustment of VCO's transistors. Analytical equations considering the body bias effect are derived for the most important relations of the VCO and then the performance is verified using the post-layout simulation results. Under a 0.16% threshold voltage shift, the sensitivity of the normalized phase noise and transconductance of the VCO with the ABB circuit compared to the constant body bias (CBB) decreases by around 8.4 times and 3.1 times, respectively. Also, the sensitivity of the normalized phase noise and transconductance of the proposed VCO under 0.16% mobility variations decreases by around 1.5 times and 1.7 times compared to the CBB, respectively. The robustness of the VCO is also examined using process variation analysis through Monte Carlo and corner case simulations. The post-layout results in the 180 nm CMOS process indicate that the proposed VCO draws a power consumption of only 398 µW from a 0.6 V supply when the VCO frequency is 2.4 GHz. It achieves a phase noise of −123.19 dBc/Hz at a 1 MHz offset and provides a figure of merit (FoM) of −194.82 dBc/Hz. [ABSTRACT FROM AUTHOR]

In this study, the anodizing process has been carried out on aluminum foil (0.20 mm thickness) by using a low voltage method. The aim of this work is to observe affect of low voltage anodizing in the surface nature of aluminum foil. The voltage was 5, 6, 7, 8, 12 and 15 V, and the duration of anodizing time was 30, 40, 50, and 60 min. The anodizing process was conducted by using 2 M aqueous sulfuric acid as an anodizing solution. The structural analysis of the oxide layer were performed by using 3D laser measurement optical microstructure. The maximum tensile load of anodized foil conduct by 5kN universal testing machine. The effect of low voltage anodizing on anodized aluminum foil microstructure, surface temperature, surface roughness, thickness, wettability, maximum tensile load, and current profile during anodizing were observed. The results obtained show that even at low voltages, the treatment has influenced the nature of the aluminum foil in terms of surface microstructure, oxide layer profile, maximum tensile load, current profile, surface temperature, wettability, and roughness.

Abstract In order to accurately extract the fault features of arc high impedance grounding of low‐voltage distribution lines and judge the fault feature types of arc high impedance grounding of low‐voltage distribution lines, a fault feature extraction method for arc high impedance grounding of low‐voltage distribution lines based on Bayesian network optimisation algorithm is proposed. According to the model of arc high impedance grounding fault based on Thomson’s principle, the parameter information of each transmission signal in arc high impedance grounding fault is extracted. Through the denoising method of arc high impedance grounding signal based on combined filter, the noise information of transmission signal in case of arc high impedance grounding fault is removed and the signal purity is improved. The detection and recognition method for fault characteristics of arc high impedance grounding of low‐voltage distribution lines based on Bayesian network optimisation algorithm is used to detect and judge the fault characteristics of the abnormal characteristics of the denoised transmission signal, and complete the fault feature extraction. After testing, this method can accurately and real‐time extract the fault characteristics of arc high impedance grounding of low‐voltage distribution lines, and has application value.

In this paper, a novel first-order delay equalizer based on a PMOS transistor is proposed which is highly suitable for the communication systems and networks. The core circuit consists of three unity-gain PMOS inverting amplifiers, one resistor and one capacitor. The newly proposed delay equalizer has ability to provide both inverting all pass and non-inverting all pass responses simultaneously from the same structure without restriction of any matching of passive elements to achieve desired performance. High input and low output impedances enable cascadability in the proposed circuit. The circuit's behaviour under loading effects and the effect of parasitic components are also examined in detail. To assess the applicability of the proposed structure, nth-order delay equalizer is also presented. The performance of the proposed work is validated through PSPICE simulations utilizing TSMC 0.18 μm level-7 CMOS technology process parameters, with voltage levels set at ±0.9 V. Furthermore, real-time post-layout verification is being carried out to ensure the confirmed performance.

Pulsed field ablation is a novel approach to treating 33.5 million patients with atrial fibrillation and offers a tissue‐specific advantage over conventional radiofrequency ablation and cryoablation. However, for complex structural targets in the heart, current electrodes often damage non‐target areas due to inaccurate ablation and have to employ electrical pulses with amplitudes of several kilovolts. Herein, materials and designs of a catheter‐integrated microelectrode and sensors that can be used for high‐precision and low‐voltage pulsed field ablation through minimally invasive operation on a large animal model, is reported. The device with a new electrode configuration supports point‐by‐point ablation with a width of 3.8 mm (≈1/10 that of a typical ablation electrode) for individual lesions at the voltage of 300 V (an order of magnitude reduction compared to the current state‐of‐the‐art). More impressively, the integrated catheter allows for pulsed field ablation on the large animal heart through minimally invasive surgery and blocks the electrical conduction pathway on the heart, which is the key to treating atrial fibrillation. This catheter‐integrated device will enhance the efficiency and safety of pulsed field ablation, especially for complex cardiac structures, thus facilitating its move to the clinic. [ABSTRACT FROM AUTHOR]

Operating at reduced voltage is an effective technique for improving the energy efficiency of computing. However, the approach is constrained by its exacerbated sensitivity to process, voltage, and temperature (PVT) variations, which under throughput constraints challenges finding the energy minimizing voltage-frequency operating point. Commonly utilized design approaches for adaptive voltage scaling are based on timing slack measurement or speculation techniques that require adding extra hardware, e.g., error detection sequence (EDS) circuits, that substantially increase the design complexity, and are not applicable for already fabricated designs. In this letter, instead of circuit-level techniques, a low-cost algorithmic error detection method is proposed as the enabler for reduced voltage operation of fast Fourier transform (FFT) accelerators. Without requiring neither gate-level nor circuit-level modifications, the method works based on an intrinsic property of the Fourier transform, i.e., Parseval’s identity. The method is demonstrated on a system-on-chip (SoC) that integrates a field-programmable gate array (FPGA) made to operate at reduced voltages. The fault detection capability is profiled using the demonstration test bench, implemented both as software and as hardware. In the experiments, a $\approx 43$ % reduction in power consumption was achieved without sacrificing the throughput and reliability. The overheads of the proposed fault detection approach scale sublinearly with respect to FFT size and are $\leq 10$ % for 1024-point FFT. [ABSTRACT FROM AUTHOR]

Low-voltage Zn-doped CuI thin film transistors (TFTs) gated by chitosan dielectric were fabricated at a low temperature. The Zn-doped CuI TFT exhibited a more superior on/off current ratio than CuI TFT due to the substitution or supplementation of copper vacancies by Zn ions. The Zn-doped CuI films were characterized by scanning electron microscope, X-ray diffraction, and X-ray photoelectron spectroscopy. The Zn-doped CuI TFTs exhibited an on/off current ratio of 1.58 × 104, a subthreshold swing of 70 mV/decade, and a field effect mobility of 0.40 cm2V−1s−1, demonstrating good operational stability. Due to the electric-double-layer (EDL) effect and high specific capacitance (17.3 μF/cm2) of chitosan gate dielectric, Zn-doped CuI TFT operates at a voltage below −2 V. The threshold voltage is −0.2 V. In particular, we have prepared Zn-doped CuI TFTs with two in-plane gates and NOR logic operation is implemented on such TFTs. In addition, using the ion relaxation effect and EDL effect of chitosan film, a simple pain neuron simulation is realized on such a p-type TFTs for the first time through the bottom gate to regulate the carrier transport of the channel. This p-type device has promising applications in low-cost electronic devices, complementary electronic circuit, and biosensors. [ABSTRACT FROM AUTHOR]

A tunable liquid crystal (LC) phase grating based on vertical-field in-plane electrical switching (VIS) is proposed. The tunable LC phase grating is composed of four parts: an LC layer, the top-plane and bottom-plane electrodes, the polyimide (PI) layer, and the top and bottom periodical strip electrodes. On the one hand, a large period LC phase grating can be obtained by applying voltage to the upper plane electrode and the lower periodic strip electrodes. On the other hand, a small period LC phase grating can be obtained by applying voltage to the lower plane electrode and the upper period electrodes. As a result, two kinds of LC phase grating with different periods can be realized by changing the driving scheme. Naturally, the diffraction angle can be adjusted by controlling different LC phase grating periods. The simulation results show that this tunable LC phase grating based on the VIS mode has a relatively short response time and low operating voltage (5.4 V). These characteristics make the tunable LC phase grating have good application prospects in holographic 3D or augmented reality (AR) display. [ABSTRACT FROM AUTHOR]

The impact detonator is a commonly used actuator for initiation ignition in all-electronic safety systems, and is the best way to solve the initiation safety of all-electronic safety systems. Aiming at the problem of high charging voltage of impact sheet detonator in the electro explication system (EFIS), the low-voltage adaptation of The Al film explosion foil with a size of 250 μm × 250 μm × 3 μm in the bridge area was studied. On the basis of analyzing the impact factors such as burst voltage, burst current and burst time in the explosion foil electric burst parameters, the correction coefficient was added to the improved FIRESET model, and the Simulink platform was used to establish a model for simulation analysis, and the change of burst current, burst voltage and burst time at 800, 1 000 and 1 200 V was studied in combination with the experimental study. The results show that when the charging voltage is 1 000 V, the electric explosion energy utilization rate of the Al explosion foil is higher, and the modified parameters added are also feasible. [ABSTRACT FROM AUTHOR]

Conventional high-performance flip-flops suffer from large power consumption at the nominal supply region and unreliable operation in the low-voltage region. To overcome these drawbacks, this paper proposes conditional-bridging flip-flops (CBFFs) that can conditionally activate the shorting device in the sense-amplifier stage. There are two versions of the proposed flip-flop. The single-ended version (CBFF-S) adopts a single-ended latching stage to optimize in terms of power consumption and area. For applications requiring high speed with differential outputs, the speed-optimized differential version (CBFF-D) is also proposed. Since the shorting device is adaptively turned on only when it is necessary, the flip-flops have fully static operations with reduced switching power consumption. The conditional bridging technique can also help minimize the effective parasitic capacitance relevant to the shorting device by relieving the design burden of weakening the device, resulting in further power reduction. The technique also provides the complete separation of complementary precharge nodes in the sense-amplifier stage during input sampling, achieving a fast and reliable operation. To further reduce power consumption and latency, the latching stage is designed to have no glitches and signal fighting and to be driven by the first stage output without signal inversion. Moreover, the conditionally bridged sense-amplifier stage having a reliable pull-down of precharge nodes and the latching stage having a contention-free operation allow the flip-flops to provide stable operation down to the near-threshold voltage (NTV) region. The proposed flip-flops were designed in a 28-nm CMOS process, whose performance evaluation results indicated that the power consumption of CBFF-S is reduced by up to 56.2% compared to conventional single-ended flip-flops at 0.1 switching activity. The minimum DQ latency was also reduced by up to 33.6%. They also indicated that CBFF-D offers up to 33.8% less power at 0.1 switching activity and up to 24.1% lower minimum DQ latency than those of conventional differential flip-flops. The resulting power-delay product (PDP) of CBFFs was at least 27.8% less than those of conventional flip-flops. The Monte-Carlo simulation results considering the process, voltage, and temperature (PVT) variations indicated that CBFFs could operate reliably down to a supply voltage of 0.3 V.

In this article, the subthreshold characteristics of a tunable single input CMOS Schmitt trigger (ST) are modeled for the first time. The high-to-low and low-to-high hysteresis transition points are analytically determined as a function of the tuning voltages and the transistors’ geometrical parameters. The derived expressions allow to design the ST with desired hysteresis width in subthreshold region. Furthermore, the proposed model allows to estimate the minimum supply voltage for which hysteresis occurs. The derived expressions also provide physical insight into the circuit behavior, by predicting the effect of supply voltage and temperature variations on the hysteresis width. The model is validated through simulations, and the maximum error between the analytical and simulated transition points is less than 5%. The model is also experimentally validated with an ASIC fabricated in AMS $0.35~\mu \text{m}$ CMOS process. The maximum error between the analytical and measured transition points is below 6%. The analytical model allows performance optimization in subthreshold region for low power applications.

A novel low-power MOS-only voltage reference is presented. The Enz–Krummenacher–Vittoz (EKV) model is adopted to provide a new perspective on the operating principle. The normalized charge density, introduced as a new variable, serves as an indicator when trimming the output temperature coefficient. The proposed voltage reference consists of a specific current generator and a 5-bit trimmable load. Thanks to the good match between the current source stage and the output stage, the nonlinear temperature dependence of carrier mobility is automatically canceled out. The circuit is designed using 55 nm COMS technology. The operating temperature ranges from −40 °C to 120 °C. The average temperature coefficient of the output voltage can be reduced to 21.7 ppm/°C by trimming. The power consumption is only 23.2 nW with a supply voltage of 0.8 V. The line sensitivity and the power supply rejection ratio at 100 Hz are 0.011 %/V and −89 dB, respectively.

A DC microgrid is an efficient way to combine diverse sources; conventional droop control is unable to achieve both accurate current sharing and required voltage regulation. This paper provides a new adaptive control approach for DC microgrid applications that satisfies both accurate current sharing and appropriate voltage regulation depending on the loading state. As the load increases in parallel, so do the output currents of the distributed generating units, and correct current sharing is necessary under severe load conditions. The suggested control approach raises the equivalent droop gains as the load level increases in parallel and provides accurate current sharing. The droop parameters were checked online and changed using the principal current sharing loops to reduce the variation in load current sharing, and the second loop also transferred the droop lines to eliminate DC microgrid bus voltage fluctuation in the adaptive droop controller, which is different and inventive. The proposed algorithm is tested using a variety of input voltages and load resistances. This work assesses the performance and stability of the suggested method using a linearized model and verifies the results using an acceptable model created in MATLAB/SIMULINK Software Version 9.3 and using Real-Time Simulation Fundamentals and hardware-based experimentation.