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This letter introduces an ultra‐low‐power temperature sensor utilizing dynamic leakage‐suppression (DLS) logic and thoroughly analyses its working principle. The sensor effectively tackles the weak pull‐up challenge inherent in DLS logic ensuring its compatibility with standard digital logic. By capitalizing on the super cut‐off attribute of DLS logic, the frontend of the sensor achieves ultra‐low power consumption, without compromising on measurement precision or the breadth of the temperature range. The digital part of the proposed utilizes the output frequency of the sensor's frontend as the clock source, in conjunction with an external 50 Hz reference clock, achieving a low overall power consumption. The frontend of the temperature sensor was fabricated using a 180 nm process, occupying a minimal area of 374 μm2${\mu }\text{m}^2$. The digital part of the circuit is implemented using FPGA. Following a two‐point calibration and system error removal, the sensor, operating at a supply voltage of 0.8 V, demonstrated a 3δ$3\delta$ error of ±0.54$\pm 0.54$∘C$^\circ\text{C}$ across the temperature range of −20 to 125 ∘C$^\circ\text{C}$. At 25 ∘C$^\circ\text{C}$, the resolution figure of merit of the sensor was 0.037 pJ K2$\text{K}^2$, with a maximum voltage sensitivity of 4.2 ∘C/V$^\circ\text{C/V}$.This letter introduces an ultra‐low‐power temperature sensor utilizing dynamic leakage‐suppression logic. Leveraging the super cut‐off feature of dynamic leakage‐suppression logic, the sensor's frontend achieves exceptionally low power consumption while maintaining high measurement accuracy and a wide temperature range. The sensor exhibits a 3δ$3\delta$ error of ±0.54$\pm 0.54$∘C$^\circ\text{C}$ after calibration and its resolution figure of merit is 0.037 pJ K2$\text{K}^2$. [ABSTRACT FROM AUTHOR]

This article will review recent progress in cryogenic CMOS designs for future scaled quantum computing applications. After introducing the scaling challenges associated with qubit control and readout electronics operating at room temperature, approaches taken to date to cryogenic control electronics design will be discussed, focusing on the most recent relevant publications. Elements of ultra-low power circuit and system design approaches for cryogenic controllers in scaled CMOS nodes (40nm to 14nm) will be reviewed, including a discussion of current state-of-the art cryogenic controller performance and power efficiency. Note that leading designs, when operated as transmon qubit state controllers, have achieved gate error rates in the range of 10-4 to 10-3 achieving spurious free dynamic range (SFDR) of ~40dB while consuming 4-23mW of power per qubit under active control, with power efficiency strongly driven by the complexity of the digital processor integrated in the controller design. These demonstrations, while significant, are just the first steps toward achieving the performance, efficiency, and scalability that will be required for future systems. This review article will discuss fundamental tradeoffs in CMOS cryogenic designs in order to address the needs of future scaled quantum computing systems. [ABSTRACT FROM AUTHOR]

Abstract This letter introduces an ultra‐low‐power temperature sensor utilizing dynamic leakage‐suppression (DLS) logic and thoroughly analyses its working principle. The sensor effectively tackles the weak pull‐up challenge inherent in DLS logic ensuring its compatibility with standard digital logic. By capitalizing on the super cut‐off attribute of DLS logic, the frontend of the sensor achieves ultra‐low power consumption, without compromising on measurement precision or the breadth of the temperature range. The digital part of the proposed utilizes the output frequency of the sensor's frontend as the clock source, in conjunction with an external 50 Hz reference clock, achieving a low overall power consumption. The frontend of the temperature sensor was fabricated using a 180 nm process, occupying a minimal area of 374 μm2. The digital part of the circuit is implemented using FPGA. Following a two‐point calibration and system error removal, the sensor, operating at a supply voltage of 0.8 V, demonstrated a 3δ error of ±0.54 ∘C across the temperature range of −20 to 125 ∘C. At 25 ∘C, the resolution figure of merit of the sensor was 0.037 pJ K2, with a maximum voltage sensitivity of 4.2 ∘C/V.

Radiological source search is a challenging task involving detection and identification of weak sources in a constantly changing radiological background. As of now, many radiological source detection algorithms have been proposed; however, their computational complexity and, hence, reliance on power intensive processing units inhibit low-power applications of radiological source search systems. In this work, we introduce the anomaly filter (AF) algorithm; a computationally light, yet effective time-series source detection algorithm based on exponential weighted moving average (EWMA) and Poisson deviance statistics. Then, we demonstrate that the proposed algorithm can be used in ensemble with other more computationally intensive source detection and identification algorithms to achieve both increased detection performance and reduced power consumption. The proposed AF algorithm and the ensemble algorithms were thoroughly benchmarked against several existing source detection and identification algorithms. The results show that the AF algorithm outperforms existing conventional source detection algorithms, and the ensemble approach improves the overall performance of existing source detection and isotope identification algorithms. Furthermore, the AF algorithm and the non-negative matrix factorization approach-based source identification (NMF-ID) algorithm were combined and implemented on a single-board microcontroller, and the power consumption was measured. This ensemble algorithm reduced the power consumption of the NMF-ID algorithm almost by a factor of 100, while improving the detection performance of the overall system.

Abstract Artificial neural networks (ANNs), inspired by the human brain's network of neurons and synapses, enable computing machines and systems to execute cognitive tasks, thus embodying artificial intelligence (AI). Since the performance of ANNs generally improves with the expansion of the network size, and also most of the computation time is spent for matrix operations, AI computation have been performed not only using the general-purpose central processing unit (CPU) but also architectures that facilitate parallel computation, such as graphic processing units (GPUs) and custom-designed application-specific integrated circuits (ASICs). Nevertheless, the substantial energy consumption stemming from frequent data transfers between processing units and memory has remained a persistent challenge. In response, a novel approach has emerged: an in-memory computing architecture harnessing analog memory elements. This innovation promises a notable advancement in energy efficiency. The core of this analog AI hardware accelerator lies in expansive arrays of non-volatile memory devices, known as resistive processing units (RPUs). These RPUs facilitate massively parallel matrix operations, leading to significant enhancements in both performance and energy efficiency. Electrochemical random-access memory (ECRAM), leveraging ion dynamics in secondary-ion battery materials, has emerged as a promising candidate for RPUs. ECRAM achieves over 1000 memory states through precise ion movement control, prompting early-stage research into material stacks such as mobile ion species and electrolyte materials. Crucially, the analog states in ECRAMs update symmetrically with pulse number (or voltage polarity), contributing to high network performance. Recent strides in device engineering in planar and three-dimensional structures and the understanding of ECRAM operation physics have marked significant progress in a short research period. This paper aims to review ECRAM material advancements through literature surveys, offering a systematic discussion on engineering assessments for ion control and a physical understanding of array-level demonstrations. Finally, the review outlines future directions for improvements, co-optimization, and multidisciplinary collaboration in circuits, algorithms, and applications to develop energy-efficient, next-generation AI hardware systems.

Highlights Dense and flat freestanding Bi2Te3-based thermoelectric nano films were successfully fabricated by sputtering technology using a newly developed nano graphene oxide membrane as a substrate. On-chip micro temperature controllers were integrated using conventional micro-electromechanical system technology, to achieve energy-efficient temperature control for low-power electronics. The tunable equivalent thermal resistance enables an ultrahigh temperature control capability of 100 K mW−1 and an ultra-fast cooling rate exceeding 2000 K s−1, as well as excellent reliability of up to 1 million cycles.

Abstract A 0.45‐V low‐power wideband image‐rejection low‐noise amplifier (LNA) using Taiwan Semiconductor Manufacturing Company (TSMC) 0.18‐μm CMOS process has been proposed. The supply voltage, power consumption and chip area of the proposed LNA can be reduced using forward body biasing, folded cascode topology and a feedback capacitor. Moreover, a wideband gain‐enhancement‐and‐image‐rejection (WGEIR) circuit including a variable resonant LC tank and a common‐gate amplifier has been developed. The inductance of the variable resonant LC tank can enlarge the gain of the proposed LNA. The capacitance of the variable resonant LC tank can achieve the image rejection. Using the WGEIR circuit, gain enhancement and wideband image rejection can be achieved simultaneously. The variable inductors and capacitors are developed for suppressing wideband image signals and good image rejection ratio (IRR). The combination of the variable inductors and capacitors can achieve eight image‐reject frequencies under three control voltages. The proposed LNA shows the measured results including a 10‐dB power gain, a 3‐dB noise figure (NF) and a −11‐dBm input third‐order intercept point (IIP3) at 2.4 GHz, respectively. The measured IRR ranges from 18 to 23 dBc around 3.6–4.5 GHz, which is 900‐MHz image‐reject bandwidth. The measured proposed LNA using the mentioned techniques consumes 0.8‐mW power.

Artificial neural networks (ANNs), inspired by the human brain's network of neurons and synapses, enable computing machines and systems to execute cognitive tasks, thus embodying artificial intelligence (AI). Since the performance of ANNs generally improves with the expansion of the network size, and also most of the computation time is spent for matrix operations, AI computation have been performed not only using the general-purpose central processing unit (CPU) but also architectures that facilitate parallel computation, such as graphic processing units (GPUs) and custom-designed application-specific integrated circuits (ASICs). Nevertheless, the substantial energy consumption stemming from frequent data transfers between processing units and memory has remained a persistent challenge. In response, a novel approach has emerged: an in-memory computing architecture harnessing analog memory elements. This innovation promises a notable advancement in energy efficiency. The core of this analog AI hardware accelerator lies in expansive arrays of non-volatile memory devices, known as resistive processing units (RPUs). These RPUs facilitate massively parallel matrix operations, leading to significant enhancements in both performance and energy efficiency. Electrochemical random-access memory (ECRAM), leveraging ion dynamics in secondary-ion battery materials, has emerged as a promising candidate for RPUs. ECRAM achieves over 1000 memory states through precise ion movement control, prompting early-stage research into material stacks such as mobile ion species and electrolyte materials. Crucially, the analog states in ECRAMs update symmetrically with pulse number (or voltage polarity), contributing to high network performance. Recent strides in device engineering in planar and three-dimensional structures and the understanding of ECRAM operation physics have marked significant progress in a short research period. This paper aims to review ECRAM material advancements through literature surveys, offering a systematic discussion on engineering assessments for ion control and a physical understanding of array-level demonstrations. Finally, the review outlines future directions for improvements, co-optimization, and multidisciplinary collaboration in circuits, algorithms, and applications to develop energy-efficient, next-generation AI hardware systems. [ABSTRACT FROM AUTHOR]

Highlights: Dense and flat freestanding Bi2Te3-based thermoelectric nano films were successfully fabricated by sputtering technology using a newly developed nano graphene oxide membrane as a substrate. On-chip micro temperature controllers were integrated using conventional micro-electromechanical system technology, to achieve energy-efficient temperature control for low-power electronics. The tunable equivalent thermal resistance enables an ultrahigh temperature control capability of 100 K mW−1 and an ultra-fast cooling rate exceeding 2000 K s−1, as well as excellent reliability of up to 1 million cycles. Multidimensional integration and multifunctional component assembly have been greatly explored in recent years to extend Moore's Law of modern microelectronics. However, this inevitably exacerbates the inhomogeneity of temperature distribution in microsystems, making precise temperature control for electronic components extremely challenging. Herein, we report an on-chip micro temperature controller including a pair of thermoelectric legs with a total area of 50 × 50 μm2, which are fabricated from dense and flat freestanding Bi2Te3-based thermoelectric nano films deposited on a newly developed nano graphene oxide membrane substrate. Its tunable equivalent thermal resistance is controlled by electrical currents to achieve energy-efficient temperature control for low-power electronics. A large cooling temperature difference of 44.5 K at 380 K is achieved with a power consumption of only 445 μW, resulting in an ultrahigh temperature control capability over 100 K mW−1. Moreover, an ultra-fast cooling rate exceeding 2000 K s−1 and excellent reliability of up to 1 million cycles are observed. Our proposed on-chip temperature controller is expected to enable further miniaturization and multifunctional integration on a single chip for microelectronics. [ABSTRACT FROM AUTHOR]

A 0.45‐V low‐power wideband image‐rejection low‐noise amplifier (LNA) using Taiwan Semiconductor Manufacturing Company (TSMC) 0.18‐μm CMOS process has been proposed. The supply voltage, power consumption and chip area of the proposed LNA can be reduced using forward body biasing, folded cascode topology and a feedback capacitor. Moreover, a wideband gain‐enhancement‐and‐image‐rejection (WGEIR) circuit including a variable resonant LC tank and a common‐gate amplifier has been developed. The inductance of the variable resonant LC tank can enlarge the gain of the proposed LNA. The capacitance of the variable resonant LC tank can achieve the image rejection. Using the WGEIR circuit, gain enhancement and wideband image rejection can be achieved simultaneously. The variable inductors and capacitors are developed for suppressing wideband image signals and good image rejection ratio (IRR). The combination of the variable inductors and capacitors can achieve eight image‐reject frequencies under three control voltages. The proposed LNA shows the measured results including a 10‐dB power gain, a 3‐dB noise figure (NF) and a −11‐dBm input third‐order intercept point (IIP3) at 2.4 GHz, respectively. The measured IRR ranges from 18 to 23 dBc around 3.6–4.5 GHz, which is 900‐MHz image‐reject bandwidth. The measured proposed LNA using the mentioned techniques consumes 0.8‐mW power. [ABSTRACT FROM AUTHOR]

A Spiking Neural Network (SNN) is realized within a 65 nm CMOS process to demonstrate the feasibility of its constituent cells. Analog hardware neural networks have shown improved energy efficiency in edge computing for real-time-inference applications, such as speech recognition. The proposed network uses a leaky integrate and fire neuron scheme for computation, interleaved with a Spike Timing Dependent Plasticity (STDP) circuit for implementing synaptic-like weights. The low-power, asynchronous analog neurons and synapses are tailored for the VLSI environment needed to effectively make use of hardware SSN systems. To demonstrate functionality, a feed-forward Spiking Neural Network composed of two layers, the first with ten neurons and the second with six, is implemented. The neuron design operates with 2.1 pJ of power per spike and 20 pJ per synaptic operation. [ABSTRACT FROM AUTHOR]

The state-of-the-art Android environment, available on a major market share of smartphones, provides an open playground for sensor data gathering. Moreover, the rise in new types of devices (e.g., wearables/smartwatches) is further extending the market opportunities with a variety of new sensor types. The existing implementations of biometric/medical sensors can allow the general public to directly access their health measurements, such as Electrocardiogram (ECG) or Oxygen Saturation (SpO2). This access greatly increases the possible applications of these devices with the combination of all the onboard sensors that are broadly in use nowadays. In this study, we look beyond the current state of the art into the positioning capacities of Android smart devices and wearables, with a focus on raw Global Navigation Satellite Systems (GNSS) measurements that are still mostly lacking in the research world. We develop a novel open-source Android application working in both smartphone and smartwatch environments for multi-sensor measurement data logging that also includes GNSS, an Inertial Navigation System (INS) magnetometer, and a barometer. Four smartphones and one smartwatch are used to perform surveys in different scenarios. The extraction of GNSS raw data from a wearable device has not been reported yet in the literature and no open-source app has existed so far for extracting GNSS data from wearables. Not only the developed app but also the results of these measurement surveys are provided as an open-access dataset. We start by defining our methodology and the acquisition protocol, and we dive into the structure of the dataset files. We also propose a first analysis of the data logged and evaluate the data according to several performance metrics. A discussion reviewing the capacities of smart devices for advanced positioning is proposed, as well as the current open challenges. [ABSTRACT FROM AUTHOR]

Abstract This paper presents a high‐precision, low‐power delta‐sigma modulator (DSM) designed for healthcare and medical diagnostics. It utilizes a hybrid switching integrator to reduce distortion caused by the non‐linear on‐resistance of switches at a low supply voltage. Leveraging the characteristics of the hybrid switching integrator, a non‐50% duty cycle sampling timing and a corresponding tunable Miller‐compensated operational transconductance amplifier are proposed to reduce resistor thermal noise and meet lower power consumption requirements. The DSM is simulated based on 130‐nm CMOS technology and achieves 93.5‐dB signal‐to‐noise‐plus‐distortion ratio at a 1‐kHz bandwidth while consuming 23.7 µW from a 1.5‐V supply.

This paper presents a high‐precision, low‐power delta‐sigma modulator (DSM) designed for healthcare and medical diagnostics. It utilizes a hybrid switching integrator to reduce distortion caused by the non‐linear on‐resistance of switches at a low supply voltage. Leveraging the characteristics of the hybrid switching integrator, a non‐50% duty cycle sampling timing and a corresponding tunable Miller‐compensated operational transconductance amplifier are proposed to reduce resistor thermal noise and meet lower power consumption requirements. The DSM is simulated based on 130‐nm CMOS technology and achieves 93.5‐dB signal‐to‐noise‐plus‐distortion ratio at a 1‐kHz bandwidth while consuming 23.7 µW from a 1.5‐V supply. [ABSTRACT FROM AUTHOR]

Abstract An ultra‐low quiescent current tri‐mode DC–DC boost converter is proposed in this paper, which can efficiently handle loads from 1 μA to 300 mA, providing 5‐V output from 3 to 4.2‐V input. Hysteresis current mode control is adopted to realize seamless mode switching between continuous conduction mode (CCM) and discontinuous conduction mode (DCM). In order to deal with the light load situation, this paper proposes a quasi burst mode (QBM). In this mode, most of the modules are turned off and only the QBM controller, low‐power current bias and sample and hold circuit are retained, which significantly reduces the static current of the converter, and thus improves the light load efficiency. Meanwhile, the average current of error amplifier and comparator are reduced significantly by dynamic biasing. Finally, the efficiency of the converter is greatly improved and kept at a reasonable output ripple. The proposed converter is implemented in a 0.13‐μm BCD process design and manufacturing. The test results show that the quiescent current of the converter is only 780 nA, which can achieve a peak efficiency of 95.6%, and ensure that the efficiency is maintained above 80% in the load range of 10 μA to 300 mA.

Abstract High step‐down DC‐DC converters require a robust and low power pre‐regulated supply for bandgap reference. This paper proposes a structure that comprised of two current paths to achieve energy efficient pre‐regulation under high and low input voltage conditions. The design eliminated large size resistors for current limiting which is usually required for high input supplies. The presented pre‐regulator structure combined with the bandgap circuit was realized with the TSMC 180‐nm BCD process. The measured results show the proposed structure has a wide input voltage range of 3.5–45 V, a temperature coefficient of 5.63 ppm/°C and typical average current consumption of 1.1 μA.

This paper presents a 9-bit differential, minimum-powered, successive approximation register (SAR) ADC intended for implantable devices or sensors. Such applications demand nanowatt-range power consumption, which is achieved by designing the SAR ADC with a proposed bootstrap switch, bespoke split-capacitive DAC, customized comparator and a modified dynamic bit-slice unit for SAR logic. The linearity of the ADC is improved by introducing a bootstrap switch with a low clock feedthrough and threshold voltage variations along with the disseminated attenuation capacitor in the split-capacitive DAC. The dynamic comparator is customized to be simple in terms of the number of transistors to gain the advantage of low power and is also designed to have a low dynamic offset voltage. The stacking concept is embedded in the bit-slice unit of SAR logic to achieve reduced leakage power. This paper is concerned with how to contribute to low power consumption in all the aspects possible related to the implementation of the SAR ADC. With a 0.4 V supply and at 2 kS/s, the proposed ADC achieves an SNDR of 52.52 dB and a power consumption of 5.29 nW, resulting in a figure of merit (FOM) of 7.66 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

Operating at reduced voltage is an effective technique for improving the energy efficiency of computing. However, the approach is constrained by its exacerbated sensitivity to process, voltage, and temperature (PVT) variations, which under throughput constraints challenges finding the energy minimizing voltage-frequency operating point. Commonly utilized design approaches for adaptive voltage scaling are based on timing slack measurement or speculation techniques that require adding extra hardware, e.g., error detection sequence (EDS) circuits, that substantially increase the design complexity, and are not applicable for already fabricated designs. In this letter, instead of circuit-level techniques, a low-cost algorithmic error detection method is proposed as the enabler for reduced voltage operation of fast Fourier transform (FFT) accelerators. Without requiring neither gate-level nor circuit-level modifications, the method works based on an intrinsic property of the Fourier transform, i.e., Parseval’s identity. The method is demonstrated on a system-on-chip (SoC) that integrates a field-programmable gate array (FPGA) made to operate at reduced voltages. The fault detection capability is profiled using the demonstration test bench, implemented both as software and as hardware. In the experiments, a $\approx 43$ % reduction in power consumption was achieved without sacrificing the throughput and reliability. The overheads of the proposed fault detection approach scale sublinearly with respect to FFT size and are $\leq 10$ % for 1024-point FFT. [ABSTRACT FROM AUTHOR]

High step‐down DC‐DC converters require a robust and low power pre‐regulated supply for bandgap reference. This paper proposes a structure that comprised of two current paths to achieve energy efficient pre‐regulation under high and low input voltage conditions. The design eliminated large size resistors for current limiting which is usually required for high input supplies. The presented pre‐regulator structure combined with the bandgap circuit was realized with the TSMC 180‐nm BCD process. The measured results show the proposed structure has a wide input voltage range of 3.5–45 V, a temperature coefficient of 5.63 ppm/°C and typical average current consumption of 1.1 μA. [ABSTRACT FROM AUTHOR]

The continued quest for finding a low‐power and high‐performance hardware algorithm for signed number multiplication led to designing a simple and novel radix‐8 signed number multiplier with 3‐bit grouping and partial product reduction performed using magnitudes of the multiplicand and the multiplier. The pre‐computation stage constitutes magnitude calculation and non‐trivial computations required to generate partial products. A new partial product reduction strategy is deployed in the design to improve the speed with low cost. 8×8, 16×16, 32×32, and 64×64 designs are presented for the proposed architectures. Performance results include area, power, delay, and power‐delay‐product of synthesized and post‐layout designs using 32 nm CMOS technology with 1.05 V supply voltage. [ABSTRACT FROM AUTHOR]

An ultra‐low quiescent current tri‐mode DC–DC boost converter is proposed in this paper, which can efficiently handle loads from 1 μA to 300 mA, providing 5‐V output from 3 to 4.2‐V input. Hysteresis current mode control is adopted to realize seamless mode switching between continuous conduction mode (CCM) and discontinuous conduction mode (DCM). In order to deal with the light load situation, this paper proposes a quasi burst mode (QBM). In this mode, most of the modules are turned off and only the QBM controller, low‐power current bias and sample and hold circuit are retained, which significantly reduces the static current of the converter, and thus improves the light load efficiency. Meanwhile, the average current of error amplifier and comparator are reduced significantly by dynamic biasing. Finally, the efficiency of the converter is greatly improved and kept at a reasonable output ripple. The proposed converter is implemented in a 0.13‐μm BCD process design and manufacturing. The test results show that the quiescent current of the converter is only 780 nA, which can achieve a peak efficiency of 95.6%, and ensure that the efficiency is maintained above 80% in the load range of 10 μA to 300 mA. [ABSTRACT FROM AUTHOR]

We introduce a novel ultra-low power system for tracking animal movements over long periods with an unprecedented high-temporal-resolution. The localization principle is based on the detection of cellular base stations using a miniaturized software-defined radio, weighing 2.0 g, including the battery, and having a size equivalent to two stacked 1-euro cent coins. Therefore, the system is small and lightweight enough to be deployed on small, wide-ranging, or migrating animals, such as European bats, for movement analysis with an unprecedented spatiotemporal resolution. The position estimation relies on a post-processing probabilistic RF pattern-matching method based on the acquired base stations and power levels. In several field tests, the system has been successfully verified, and a run-time of close to one year has been demonstrated. [ABSTRACT FROM AUTHOR]

This is the first review of conductive electrets (unpoled carbons and metals), which provide a new avenue for low-power electronics. The electret provides low DC voltage (μV) while allowing low DC current (μA) to pass through. Ohm's Law is obeyed. The voltage scales with the inter-electrode distance. Series connection of multiple electret components provides a series voltage that equals the sum of the voltages of the components if there is no bending at the connection between the components. Otherwise, the series voltage is below the sum. Bending within the component also diminishes the voltage because of the polarization continuity decrease. The electret originates from the interaction of a tiny fraction of the carriers with the atoms. This interaction results in the charge in the electret. Dividing the electret charge by the electret voltage V' provides the electret-based capacitance C', which is higher than the permittivity-based capacitance (conventional) by a large number of orders of magnitude. The C' governs the electret energy (1/2 C'V'2) and electret discharge time constant (RC', where R = resistance), as shown for metals. The discharge time is promoted by a larger inter-electrode distance. The electret discharges occur upon short-circuiting and charge back upon subsequent opencircuiting. The discharge or charge of the electret amounts to the discharge or charge of C'. [ABSTRACT FROM AUTHOR]

An energy-independent wearable electronic system is being researched, where the energy required for its operation is obtained from human body movements and heat flow. The system power source consists of an electromagnetic motion energy harvester (mass up to 70 g, peak power reaching 38 mW depending on the intensity of movement), a thermoelectric harvester (mass 112 g, peak power up to 3 mW), power converters and a storage capacitor. The functional part of the system consists of a temperature and humidity sensors and a wireless data transmission module, while the energy-aware power management and the main function control is accomplished by a microcontroller, maintaining a safe input voltage range by adjusting the average consumption of the device. Only off-the-shelf components that provide greater configurability and could utilize a broader harvested voltage range were used. This study demonstrates that using a common energy storage element provides an energy flow stabilization effect that reduces the overall power instability, which can be a limiting factor for a single energy harvester system. The prototype was tested in controlled environment by walking on a treadmill and provided the necessary amount of energy for a sustained system operation even during motion pauses. Electrical energy storage efficiency of the system averaged at 17 %, with a peak efficiency reaching 21 %.

Abstract This article presents the design and optimisation of a sub‐1 GHz class‐F ultra‐low power (ULP) power amplifier (PA) in 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. An envelope tracking (ET) supply biasing technique is adopted to improve the efficiency of class‐F PA. The ET consist of a pre‐amp right before the detector in order to enhance the efficiency and save adequate amount of dc power consumption. The PA consists of two cascode cells terminated as class‐F with gate‐to‐drain feedback in order to enhance linearity and limit any harmonic component from the input signal. The novel design consumes a dc power of 3.75 mW, power added efficiency of 37.1%, operating at 915–925 MHz unlicensed band and total saturated output power of 22 dBm including 14 dBm power gain at PA, which qualifies under long‐range low power wireless local area network IEEE 802.11ah standard. The inductor‐less design for ET supply bias reduces the chip layout size to 0.13 mm2 only.

This paper presents a nanowatt CMOS voltage reference (VR) with ultra‐low line sensitivity (LS) and high‐power supply ripple rejection (PSRR). The proposed VR consists of two simple nanowatt two‐transistor (2T) VRs. Two current mirrors are associated with these VRs. The outputs of the current mirrors have different magnitudes but the same power supply dependence slope. For this purpose, the primary 2T VR has been designed with long‐channel MOSFETs, while the secondary VR utilizes medium‐channel length transistors. Low dependence on the power supply variations is achieved by subtracting these two currents, whereas the subtracted current is almost independent of the power supply. The temperature coefficient (TC) minimization is achieved separately by adjusting the transistor sizes of the primary VR. Post‐layout simulation is performed using 0.18 µm standard CMOS technology, which shows a nominal output voltage of 0.15 V, obtaining an average TC of 21.4 ppm/°C over a temperature range of 0–120°C. It achieves an excellent line sensitivity of 0.0039%/V when the supply voltage varies from 0.4 to 2 V. The dc PSRR values at 0.4 and 1 V of supply voltage are −80.1 and ‐114.2 dB, respectively at room temperature. [ABSTRACT FROM AUTHOR]

A true‐time delay (TTD) cell in TSMC 0.18 μm CMOS technology for 1–5 GHz applications is presented. Process variations, ageing effects, field variations, and other non‐idealities have some impacts on the TTD cell's devices. One of the vulnerable specifications of TTD cells is their delay variation. While the TTD cell works in a delay line, the cell must have a constant and robust delay in the frequency band. For this matter, the body bias technique is presented and applied to the inductor‐less TTD cell. With this technique, the threshold voltage can be manipulated intentionally. So, any variation in this voltage can be compensated with the body biasing of transistors. The simulation results show the TTD cell's robust performance against non‐idealities, while delay variation improves more than 3× times in the frequency band of interest. This TTD cell provides a 50.95 pS delay with only 2% variation, while S11 and S22 parameters are lower than −10 dB in the 1–5 GHz frequency band. IIP3 of the TTD cell is about 2.7 dBm, and the power consumption is 20.5 mW. [ABSTRACT FROM AUTHOR]

An ultra‐low‐energy SRAM composed of single‐ended cells is demonstrated on silicon in this investigation. More specifically, the supply voltages of cells are gated by wordline (WL) enable, and the voltage mode select (VMS) signals select one of the corresponding supply voltages. A lower voltage is selected to maintain stored bit state when cells are not accessed, lowering the standby power. And when selecting a cell (i.e. WL is enabled) to perform the read or write (R/W) operations, the normal supply voltage is used. A 1‐kb SRAM prototype based on the single‐ended cells with built‐in self‐test (BIST) and power‐delay production (PDP) reduction circuits was realised on silicon using 40‐nm CMOS technology. Theoretical derivations and simulations of all‐PVT‐corner variations are also disclosed to justify low energy performance. Physical measurements of six prototypes on silicon shows that the energy per bit is 1.0 fJ at the 10 MHz system clock. [ABSTRACT FROM AUTHOR]

Abstract The continued quest for finding a low‐power and high‐performance hardware algorithm for signed number multiplication led to designing a simple and novel radix‐8 signed number multiplier with 3‐bit grouping and partial product reduction performed using magnitudes of the multiplicand and the multiplier. The pre‐computation stage constitutes magnitude calculation and non‐trivial computations required to generate partial products. A new partial product reduction strategy is deployed in the design to improve the speed with low cost. 8×8, 16×16, 32×32, and 64×64 designs are presented for the proposed architectures. Performance results include area, power, delay, and power‐delay‐product of synthesized and post‐layout designs using 32 nm CMOS technology with 1.05 V supply voltage.

Abstract A low‐power wideband self‐biased phase‐locked loop (SPLL) is proposed for multi‐protocol SerDes applications in this letter. With the proposed adaptive fast‐locking current circuit (AFLCC) and self‐biased charge pump (CP), the settling time is reduced significantly, and no extra power and jitter contribution. In addition, a start‐up module is adopted to reset the system to an optimal initial operating frequency quickly. The proposed 1‐3‐GHz SPLL, fabricated in TSMC 28‐nm CMOS process, occupies a compact 0.028 mm2 area. It achieves a roughly constant settling time of 5 μs over all frequencies and division ratios range. Only 0.96 mW is consumed at 1 GHz frequency.

Suppression of electronic defects induced by GeO x at the high- k gate oxide/SiGe interface is critical for implementation of high-mobility SiGe channels in complementary metal-oxide-semiconductor (CMOS) technology. Theoretical and experimental studies have shown that a low defect density interface can be formed with an SiO x-rich interlayer on SiGe. Experimental studies in the literature indicate a better interface formation with Al2O3 in contrast to HfO2 on SiGe; however, the mechanism behind this is not well understood. In this study, the mechanism of forming a low defect density interface between Al2O3/SiGe is investigated using atomic layer deposited (ALD) Al2O3 insertion into or on top of ALD HfO2 gate oxides. To elucidate the mechanism, correlations are made between the defect density determined by impedance measurements and the chemical and physical structures of the interface determined by high-resolution scanning transmission electron microscopy and electron energy loss spectroscopy. The compositional analysis reveals an SiO x rich interlayer for both Al2O3/SiGe and HfO2/SiGe interfaces with the insertion of Al2O3 into or on top of the HfO2 oxide. The data is consistent with the Al2O3 insertion inducing decomposition of the GeO x from the interface to form an electrically passive, SiO x rich interface on SiGe. This mechanism shows that nanolaminate gate oxide chemistry cannot be interpreted as resulting from a simple layer-by-layer ideal ALD process, because the precursor or its reaction products can diffuse through the oxide during growth and react at the semiconductor interface. This result shows that in scaled CMOS, remote oxide ALD (oxide ALD on top of the gate oxide) can be used to suppress electronic defects at gate oxide semiconductor interfaces by oxygen scavenging.

Long-Range (LoRa) transmission technology is potentially a suitable solution in abundant applications such as smart cities, smart industries, smart health, and others, although it is challenging and complex to implement. LoRa is a non-cellular modulation technology for Long-Range Wide-Area Networks (LoRaWAN) and is suitable for Internet of Things (IoT) solutions through its long-range and low-power consumption characteristics. The present paper provides a comprehensive analysis of LoRa wireless transactions through several measurements, which differ in LoRa parameter configuration. The results showed dependency of the power consumed by the transaction on the selected Effective Isotropic Radiated Power (EIRP). The quantity of energy consumed by the transaction also significantly depends on the selected data rate (combination of the spread factor and bandwidth) and payload.

Abstract This paper presents a nanowatt CMOS voltage reference (VR) with ultra‐low line sensitivity (LS) and high‐power supply ripple rejection (PSRR). The proposed VR consists of two simple nanowatt two‐transistor (2T) VRs. Two current mirrors are associated with these VRs. The outputs of the current mirrors have different magnitudes but the same power supply dependence slope. For this purpose, the primary 2T VR has been designed with long‐channel MOSFETs, while the secondary VR utilizes medium‐channel length transistors. Low dependence on the power supply variations is achieved by subtracting these two currents, whereas the subtracted current is almost independent of the power supply. The temperature coefficient (TC) minimization is achieved separately by adjusting the transistor sizes of the primary VR. Post‐layout simulation is performed using 0.18 µm standard CMOS technology, which shows a nominal output voltage of 0.15 V, obtaining an average TC of 21.4 ppm/°C over a temperature range of 0–120°C. It achieves an excellent line sensitivity of 0.0039%/V when the supply voltage varies from 0.4 to 2 V. The dc PSRR values at 0.4 and 1 V of supply voltage are −80.1 and ‐114.2 dB, respectively at room temperature.

The event sensor provides high temporal resolution and generates large amounts of raw event data. Efficient low-complexity coding solutions are required for integration into low-power event-processing chips with limited memory. In this paper, a novel lossless compression method is proposed for encoding the event data represented as asynchronous event sequences. The proposed method employs only low-complexity coding techniques so that it is suitable for hardware implementation into low-power event-processing chips. A first, novel, contribution consists of a low-complexity coding scheme which uses a decision tree to reduce the representation range of the residual error. The decision tree is formed by using a triplet threshold parameter which divides the input data range into several coding ranges arranged at concentric distances from an initial prediction, so that the residual error of the true value information is represented by using a reduced number of bits. Another novel contribution consists of an improved representation, which divides the input sequence into same-timestamp subsequences, wherein each subsequence collects the same timestamp events in ascending order of the largest dimension of the event spatial information. The proposed same-timestamp representation replaces the event timestamp information with the same-timestamp subsequence length and encodes it together with the event spatial and polarity information into a different bitstream. Another novel contribution is the random access to any time window by using additional header information. The experimental evaluation on a highly variable event density dataset demonstrates that the proposed low-complexity lossless coding method provides an average improvement of 5.49 % , 11.45 % , and 35.57 % compared with the state-of-the-art performance-oriented lossless data compression codecs Bzip2, LZMA, and ZLIB, respectively. To our knowledge, the paper proposes the first low-complexity lossless compression method for encoding asynchronous event sequences that are suitable for hardware implementation into low-power chips. [ABSTRACT FROM AUTHOR]

The Internet of Things revolution requires a low-cost, stable, and highly efficient power source to allow autonomous operation of smart objects and wireless sensors even at very low light levels. Indoor photovoltaics (PV) has the potential to fulfil these requirements, providing independence from the main grid, portability, and improved sustainability for low-consumption devices. Whereas polycrystalline silicon dominates the outdoor solar cell market, amorphous silicon is commercially more suited for products used inside buildings, delivering higher efficiencies under indoor illumination (with its extremely lower intensities and narrower spectra compared to sunlight). In very recent years, there has been a remarkable rise in the research and development of new generation photovoltaic solar cells, i.e., those based on organic, dye-sensitized and perovskite absorbers, focused on indoor applications with efficiencies rising well above those possible under the sun reaching and even surpassing the 30 % power conversion efficiency threshold. This review provides a systematic overview of indoor PV devices, highlighting the main progress achieved and the strategies to design highly efficient cells as well as the issues to be resolved for this field to continue to prosper. We also analyse the differences in device design for solar cells meant for operation in the outdoors vs indoors. Markets and applications to be tapped by indoor photovoltaics for light harvesting are huge, ranging from building-integrated elements to consumer products, biomedical devices, wireless sensors and communication technologies. [Display omitted] • Latest developments in indoor PV and market potential across all PV technologies, established and emerging, are explored. • Indoor PV devices and performances are analysed through the lenses of material, device, and interface engineering. • Both positive trends and critical issues that are emerging in the field of indoor PV are addressed. • Guidance for identifying significant differences in design and operation of PV devices for outdoor vs indoor is provided. [ABSTRACT FROM AUTHOR]

A Spiking Neural Network (SNN) is realized within a 65 nm CMOS process to demonstrate the feasibility of its constituent cells. Analog hardware neural networks have shown improved energy efficiency in edge computing for real-time-inference applications, such as speech recognition. The proposed network uses a leaky integrate and fire neuron scheme for computation, interleaved with a Spike Timing Dependent Plasticity (STDP) circuit for implementing synaptic-like weights. The low-power, asynchronous analog neurons and synapses are tailored for the VLSI environment needed to effectively make use of hardware SSN systems. To demonstrate functionality, a feed-forward Spiking Neural Network composed of two layers, the first with ten neurons and the second with six, is implemented. The neuron design operates with 2.1 pJ of power per spike and 20 pJ per synaptic operation.

Abstract In recent years, the use of memristors in circuits design has rapidly increased and attracted research interest. Advances have been made to both the size and the complexity of memristor designs. Therefore, computer aided design tools are required to handle memristor‐based large‐scale designs. A comprehensive automatic framework for the design and synthesis of large‐scale memristor‐complementary metal‐oxide‐semiconductor (CMOS) circuits is described herein. This framework provides a synthesis approach that can be applied to all memristor‐based digital logic designs. In particular, it is a proposal for a characterization methodology of memristor‐based logic cells to generate a standard cell library file for large‐scale simulation. The proposed architecture is based on RRAM and ReRAM redox‐based devices and the memristor ratioed logic design approach. The proposed framework is implemented in the Cadence Virtuoso schematic‐level environment and was verified with Verilog‐XL, MATLAB, and the electronic design automation synopses compiler after being translated to the behavioral level. The proposed method can be applied to implement any digital logic design. Nevertheless, it is perfectly suitable for signal processing applications that require MATLAB functions to produce text files with hex values in order to overcome the limitations of the simulation environment. A framework is deployed herein for design of the memristor‐based parallel 8‐bit adder/subtractor and a 2D memristive‐based median filter. Both proposed designs memristor‐based adder/subtractor and memristive median filter have significant power reductions of 66% and 16% respectively, when compared to the same designs using CMOS technology.

A low‐power wideband self‐biased phase‐locked loop (SPLL) is proposed for multi‐protocol SerDes applications in this letter. With the proposed adaptive fast‐locking current circuit (AFLCC) and self‐biased charge pump (CP), the settling time is reduced significantly, and no extra power and jitter contribution. In addition, a start‐up module is adopted to reset the system to an optimal initial operating frequency quickly. The proposed 1‐3‐GHz SPLL, fabricated in TSMC 28‐nm CMOS process, occupies a compact 0.028 mm2 area. It achieves a roughly constant settling time of 5 μs over all frequencies and division ratios range. Only 0.96 mW is consumed at 1 GHz frequency. [ABSTRACT FROM AUTHOR]

We present a high-power conversion efficiency (PCE) on-chip switched-capacitor (SC) DC–DC step-up converter for a fully implantable neural interface operating with less than a few tens µW from energy harvesting. To improve the PCE in such light loads and wide variations of voltage-conversion ratio (VCR), which is a typical scenario for ultra-low-power fully implantable systems depending on energy harvesting, a phase-reduced soft-charging technique has been implemented in a step-up converter, thereby achieving very low VCR-sensitive PCE variation compared with other state-of-the-art works. The proposed DC–DC converter has been fabricated in a standard 180 nm CMOS 1P6M process. It exhibits high PCE (~80%) for wide input and output ranges from 0.5 V to 1.2 V and from 1.2 V to 1.8 V, respectively, with switching frequencies of 0.3–2 MHz, achieving a peak efficiency of 82.6% at 54 µW loads. [ABSTRACT FROM AUTHOR]

A novel inhibitable and firing threshold voltage tunable vertical nanowire (NW) single transistor neuron device with core–shell dual-gate (CSDG) was realized and verified by TCAD simulation. The CSDG NW neuron is enclosed by an independently accessed shell gate and core gate to serve an excitatory–inhibitory transition and a firing threshold voltage adjustment, respectively. By utilizing the shell gate, the firing of specific neuron can be inhibited for winner-takes-all learning. It was confirmed that the independently accessed core gate can be used for adjustment of the firing threshold voltage to compensate random conductance variation before the learning and to fix inference error caused by unwanted synapse conductance change after the learning. This threshold voltage tuning can also be utilized for homeostatic function during the learning process. Furthermore, a myelination function which controls the transmission rate was obtained based on the inherent asymmetry between the source and drain in vertical NW structure. Finally, using the CSDG NW neuron device, a letter recognition test was conducted by SPICE simulation for a system-level validation. This multi-functional neuron device can contribute to construct a high-density monolithic SNN hardware combining with the previously developed vertical synapse MOSFET devices. [ABSTRACT FROM AUTHOR]

Abstract A self‐timed microarchitecture called KeyRing is presented, and a method for implementing KeyRing circuits compatible with a timing‐driven electronic design automation (EDA) flow is discussed. The KeyRing microarchitecture is derived from the AnARM, a low‐power self‐timed ARM processor based on ad hoc design principles. First, the unorthodox design style and circuit structures are revisited. A theoretical model that can support the design of generic circuits and the elaboration of EDA methods is then presented. Also addressed are the compatibility issues between KeyRing circuits and timing‐driven EDA flows. The proposed method leverages relative timing constraints to translate the timing relations in a KeyRing circuit into a set of timing constraints that enable timing‐driven synthesis and static timing analysis. Finally, two 32‐bit RISC‐V processors are presented; called KeyV and based on KeyRing microarchitectures, they are synthesized in a 65 nm technology using the proposed EDA flow. Postsynthesis results demonstrate the effectiveness of the design methodology and allow comparisons with a synchronous alternative called SynV. Performance and power consumption evaluations show that KeyV has a power efficiency that lies between SynV with clock‐gating and SynV without clock‐gating.

Abstract Digital‐to‐analogue converters (DACs) are essential blocks for interfacing the digital environment with the real world. A novel architecture, using a digital‐to‐time converter (DTC) and a time‐to‐voltage converter (TVC), is employed to form a low‐power time‐based DAC (T‐DAC) that fits low‐power low‐speed applications. This novel conversion mixes the digital input code into a digital pulse width modulated (D‐PWM) signal through the DTC circuit, then converts this D‐PWM signal into an analogue voltage through the TVC circuit. This new T‐DAC is not only an energy‐efficient design but also an area‐efficient implementation. Power optimization is achieved by controlling the supply voltage of the TVC circuit with a discontinuous waveform using a low bias current. Moreover, the implementation area is optimized by proposing a new DAC architecture with a coarse‐fine DTC circuit. Post‐layout simulations of the proposed T‐DAC is conducted using industrial hardware‐calibrated 0.13 μm. Complementary metal oxide semiconductor technology with a 1 V supply voltage, 1 MS/s conversion rate, and 0.9 μW power dissipation.

Abstract An energy‐efficient regenerative comparator design is unveiled. A floating capacitor is utilized to protect the complete discharge of the preamplifier output nodes by NMOS input transistors. The introduced floating capacitor is flipped around the preamplifier to allow PMOS cross‐couple transistor charge reutilization and elevate amplification gain at the integration phase. By increasing amplification gain, the input common mode voltage of the NMOS latch that is toggled within some delay is increased, too. Therefore, the latch stage is activated strongly, and regeneration delay is reduced. Simulation results corroborate that the proposed technique reduces power consumption and input‐referred offset by more than 60% compared with results of similar previous works. Furthermore, the referred noise and delay are improved more than 30%.

Abstract This study presents a numerical analysis to correlate performance characteristics of indoor photovoltaic (PV) devices with those of DC‐to‐DC up‐converters designed for low‐power electronic applications. A theoretical model based on self‐consistent solution of Poisson's equation and continuity equation under optical generation‐recombination conditions has been applied to design Cu2ZnSn(SSe)4‐based PV devices having type‐I and type‐II energy band profiles, such that they can operate with peak efficiencies of 12.6% and 14.1%, respectively, under illumination from an experimentally characterized white light‐emitting diode. Each PV device has been subsequently utilized as the input source of a Meissner oscillator‐based self‐driven DC‐to‐DC converter. Comparative analysis shows that in spite of the lower PV conversion efficiency, the PV device having higher short‐circuit current density results in a higher output efficiency of the converter circuit. Similar characteristic trends are obtained for a boost converter operating in a discontinuous conduction mode, whereas a continuous conduction mode of operation results in the opposite trend. The underlying reason behind such an observation has been traced back to the transient behaviour of the inductor current of the converter. The results of this study suggest close correlation between physics‐based design parameters of the PV device and output performance characteristics of the converter circuit.

Abstract As one of the most critical blocks of the CMOS image sensor (CIS), the accuracy and power consumption of the analogue‐to‐digital converter (ADC) play an important role in its performance. However, due to the mutually restrictive relationship between power consumption and accuracy in the single‐slope ADC (SS ADC), it is difficult to improve these performance indexes meantime without an efficient optimal design method. Here, an optimal design methodology based on an improved artificial fish swarm optimization algorithm (IAFSOA) is proposed for a 10‐bit SS ADC in CIS. First, a voltage storage structure and offset calibration circuit are developed for promoting the performance of the comparator. Then, IAFSOA is developed for the circuit parameters optimization with faster convergence rate and higher computational accuracy. The proposed multi‐objectives optimization algorithm can obtain the optimal parameters of the kernel circuit components and lead to an enhancement of both power consumption and accuracy. The optimized SS ADC is designed based on 0.18 µm process to verify the effectiveness of the proposed method. Compared to the earlier reported work, the IAFSOA‐based optimal design method can promote the performance of the SS ADC by an improvement of effective number of bits and a reduction of power consumption.

Abstract The authors have proposed an inverter resistor capacitor (IRC)‐based simple chaotic ring oscillator with dual feedback for the generation of the chaotic waveform. The proposed chaotic system uses three coupled autonomous first‐order differential equations and it can be electrically demonstrated using the complementary metal oxide semiconductor (CMOS) inverters with few passive RC elements for the generation of the high‐frequency strange attractor. The basic dynamical characteristics and multistability property with complex bifurcation pattern in a wide range of parameters are well observed through theoretical as well as numerical simulation analysis using scaled inverse tangent function. In addition, a simple IRC chaotic model design is investigated using 0.18μm MOS transistor parameters with grounded capacitors and an equivalent CMOS‐based scaled inverse tangent function. Moreover, the Cadence post layout simulation gives useful information about the circuit sustainability for IC design with high frequency (MHz), low power dissipation (940 μW) and small chip area (826.3 μm2).

Abstract In order to cut the costs and overcome the leakage current of batteries caused in traditional method, this study introduces an improved voltage transfer method for lithium battery string management chip. This proposed circuit based on the improved voltage transfer method is fabricated in 180‐nm Bipolar‐CMOS‐DMOS is correct technology, and has been successfully applied to a three lithium batteries string management chip. These measurements indicate that this circuit transfers each cell’s voltage reliably and adopt protection against abnormal conditions. Furthermore, analysis of 50 samples shows that the improved method can greatly eliminate the battery leakage. The circuit reduces the leakage current to nanoampere scale and is integrated into the lithium battery string management chip, which is helpful for battery voltage balance and low cost.

Abstract This study presents a 4.6–12.8 GHz injection‐locked frequency divider (ILFD) based on modified varactor‐less Colpitts oscillator topology. A modified Colpitts ILFD is proposed to improve the LR and reduces power consumption, simultaneously. Meanwhile, the forward body bias technique is utilized to further decrease power consumption. Based on the 55 nm CMOS technology, a modified varactor‐less Colpitts ILFD with a free‐running frequency of 4.05 GHz is implemented. The proposed modified varactor‐less Colpitts ILFD exhibits 94.3% LR from 4.6 to 12.8 GHz with an injection power of 0 dBm. It consumes 2.7 mW power from 0.6 V supply voltage and the core area is 0.38 mm2.