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97 results on '"Lu Pingjing"'

5. The Evolution of Supercomputer Architecture: A Historical Perspective

Author

Li, Bao, Lu, Pingjing, Diniz Junqueira Barbosa, Simone, Series editor, Chen, Phoebe, Series editor, Du, Xiaoyong, Series editor, Filipe, Joaquim, Series editor, Kara, Orhun, Series editor, Liu, Ting, Series editor, Kotenko, Igor, Series editor, Sivalingam, Krishna M., Series editor, Washio, Takashi, Series editor, Xu, Weixia, editor, Xiao, Liquan, editor, Li, Jinwen, editor, and Zhang, Chengyi, editor

Published
2016
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8. Scalable NIC Architecture to Support Offloading of Large Scale MPI Barrier

Author

Wang, Shaogang, Xu, Weixia, Wu, Dan, Pang, Zhengbin, Lu, Pingjing, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Wu, Chenggang, editor, and Cohen, Albert, editor

Published
2013
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9. The Evaluation and Optimization of 3-D Jacobi Iteration on a Stream Processor

Author

Zhang, Ying, Li, Gen, Li, Yongjin, Sun, Caixia, Lu, Pingjing, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Park, James J. (Jong Hyuk), editor, Arabnia, Hamid R., editor, Kim, Cheonshik, editor, Shi, Weisong, editor, and Gil, Joon-Min, editor

Published
2013
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10. A SyncML Middleware-Based Solution for Pervasive Relational Data Synchronization

Author

Yang, Haitao, Yang, Peng, Lu, Pingjing, Wang, Zhenghua, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Cao, Jian, editor, Li, Minglu, editor, Wu, Min-You, editor, and Chen, Jinjun, editor

Published
2008
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11. µFuncCache: A User-Side Lightweight Cache System for Public FaaS Platforms.

Author

Li, Bao, Li, Zhe, Luo, Jun, Tan, Yusong, and Lu, Pingjing

Subjects
PUBLIC architecture, QUALITY of service, DATABASES, USER experience, MUNICIPAL services, CLOUD computing
Abstract

Building cloud-native applications based on public "Function as a Service" (FaaS) platforms has become an attractive way to improve business roll-out speed and elasticity, as well as reduce cloud usage costs. Applications based on FaaS are usually designed with multiple different cloud functions based on their functionality, and there will be call relationships between cloud functions. At the same time, each cloud function may depend on other services provided by cloud providers, such as object storage services, database services, and file storage services. When there is a call relationship between cloud functions, or between cloud functions and other services, a certain delay will occur, and the delay will increase with the length of the call chain, thereby affecting the quality of application services and user experience. Therefore, we introduce μFuncCache, a user-side lightweight caching mechanism to speed up data access for public FaaS services, fully utilizing the container delay destruction mechanism and over-booked memory commonly found in public FaaS platforms, to reduce function call latency without the need to perceive and modify the internal architecture of public clouds. Experiments in different application scenarios have shown that μFuncCache can effectively improve the performance of FaaS applications by consuming only a small amount of additional resources, while achieving a maximum reduction of 97% in latency. [ABSTRACT FROM AUTHOR]

Published
2023
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12. Brief introduction of TianHe exascale prototype system

Author

Wang, Ruibo, primary, Lu, Kai, additional, Chen, Juan, additional, Zhang, Wenzhe, additional, Li, Jinwen, additional, Yuan, Yuan, additional, Lu, Pingjing, additional, Huang, Libo, additional, Li, Shengguo, additional, and Fan, Xiaokang, additional

Published
2021
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13. MPLEG: A Multi-mode Physical Layer Error Generator for Link Layer Fault Tolerance Test

Author

Yi Dai, Lai Mingche, Xingyun Qi, Lu Pingjing, Cao Jijun, and Chang Junsheng

Subjects
Generator (computer programming), Computer science, Physical layer, Link layer, Fault tolerance, Integrated circuit design, Chip, Engineering design process, Simulation, FPGA prototype
Abstract

In the design of high-speed communication network chips, the fault-tolerant design of the link layer is among the most important parts. In the design process, the link layer fault tolerance function need to be fully tested and verified. But it is far from enough to rely only on traditional case-by-case simulation. In order to test and verify this function completely, this paper proposes a configurable multi-mode physical layer error generation method implemented on chip: MPLEG (a Multi-mode Physical Layer Error Generator). With MPLEG, a desired bit error pattern can be generated at the physical layer in all stages of chip design, including simulation verification, FPGA prototype system verification, sample chip testing, and actual system running. The statistical analysis of the experimental results shows that MPLEG can generate an error pattern almost identical to the real link error. Meanwhile, MPLEG can perform relatively complete and efficient testing and verification of various functions of link layer fault tolerance.

Published
2020

17. Nonpharmacological Interventions for Depressive Symptoms in End-Stage Renal Disease: A Systematic Review.

Author

Wen, Xin, Wang, Yu, Zhao, Qiuge, Zhang, Hongrui, Shi, Huage, Wang, Mengmeng, and Lu, Pingjing

Subjects
CHRONIC kidney failure, CONFIDENCE intervals, MENTAL depression, INFORMATION storage & retrieval systems, MEDICAL databases, MEDICAL information storage & retrieval systems, MEDLINE, ONLINE information services, SYSTEMATIC reviews
Abstract

Depressive symptoms are common in patients with end-stage renal disease, which can affect treatment and prognosis. We aimed to evaluate the effects of nonpharmacological interventions for depressive symptoms in end-stage renal disease. Eligible studies were identified using PubMed, Web of Science, the Cochrane Library, Embase, and PsycNET (up to March 2019). We identified 24 studies including 1,376 patients. We found that psychological intervention (−0.60, 95% confidence interval [CI] = [–0.87, –0.33]), exercise (−1.13, 95% CI = [–1.56, –0.69]), and manual acupressure (−0.26, 95% CI = [–0.50, 0.03]) were associated with a significant effect on depressive symptoms. However, few studies reported adverse events, and conclusions about safety should be drawn cautiously. While the available data show that nonpharmacological interventions are potential strategies to alleviate depressive symptoms of patients with end-stage renal disease, recommendation of the most efficacious interventions for this population will require future randomized controlled trials with large-scale, long-term intervention. [ABSTRACT FROM AUTHOR]

Published
2020
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18. Hardware Acceleration of Barrier Communication for Large Scale Parallel Computer

Author

Lu Pingjing, Pang Zhengbin, Wu Dan, and Wang Shaogang

Subjects
Computer science, Message passing, Scalability, Hardware acceleration, Parallel computing
Abstract

MPI collective communication overhead dominates the communication cost for large scale parallel computers, scalability and operation latency for collective communication is critical for next generation computers. This paper proposes a fast and scalable barrier communication offload approach which supports millions of compute cores. Following our approach, the barrier operation sequence is packed by host MPI driver into the barrier “descriptor”, which is pushed to the NIC (Network-Interfaces). The NIC can complete the barrier automatically following its algorithm descriptor. Our approach accelerates both intra-node and inter-node barrier communication. We show that our approach achieves both barrier performance and scalability, especially for large scale computer system. This paper also proposes an extendable and easy-to-implement NIC architecture supporting barrier offload communication and also other communication pattern.

Published
2013

20. Optimizing Private Memory Performance by Dynamically Deactivating Cache Coherence

Author

Wu Dan, Xu Weixia, Lu Pingjing, Wang Shaogang, Dai Yi, and Pang Zhengbin

Subjects
Memory coherence, CPU cache, Cache coloring, Computer science, Real-time computing, Cache pollution, Non-uniform memory access, Write-once, Cache invalidation, Interleaved memory, Cache algorithms, Distributed shared memory, Hardware_MEMORYSTRUCTURES, business.industry, MESI protocol, Cache-only memory architecture, Uniform memory access, Memory map, MESIF protocol, Memory management, Shared memory, Bus sniffing, Cache, business, Cache coherence, Computer network
Abstract

User Program has significant percentage of memory requests that target only private data, which does not need to resolve cache coherence conflicts. Yet traditional coherence protocol does not distinguish between shared and private blocks, which leaves much optimization space for memory reference latency and power consumption. This paper proposes an optimized cache coherence protocol, called PMESI, which dynamically deactivates cache coherence maintenance for private memory space. PMESI achieves two distinguishing features: the reduction of memory access latency and system power consumption. Simulation results on the cycle accurate simulator for wide range of industry benchmarks show that 54\% memory references can be efficiently optimized and program execution time is reduced 9\% on average.

Published
2012

31. Hardware Acceleration of Barrier Communication for Large Scale Parallel Computer.

Author

Pang Zhengbin, Wang Shaogang, Wu Dan, and Lu Pingjing

Abstract

MPI collective communication overhead dominates the communication cost for large scale parallel computers, scalability and operation latency for collective communication is critical for next generation computers. This paper proposes a fast and scalable barrier communication offload approach which supports millions of compute cores. Following our approach, the barrier operation sequence is packed by host MPI driver into the barrier “descriptor”, which is pushed to the NIC (Network-Interfaces). The NIC can complete the barrier automatically following its algorithm descriptor. Our approach accelerates both intra-node and inter-node barrier communication. We show that our approach achieves both barrier performance and scalability, especially for large scale computer system. This paper also proposes an extendable and easy-to-implement NIC architecture supporting barrier offload communication and also other communication pattern. [ABSTRACT FROM PUBLISHER]

Published
2013
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