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The increasing impact of interconnections on overall circuit performance makes timing-driven placement (TDP) a crucial step toward timing closure. Current TDP techniques improve critical paths but overlook the impact of register placement on clock tree quality. On the other hand, register placement techniques found in the literature mainly focus on power consumption, disregarding timing and routabilty. Indeed, postponing register placement may undermine the optimization achieved by TDP, since the wiring between sequential and combinational elements would be touched. This work proposes a new approach for an effective coupling between register placement and TDP that relies on two key aspects to handle sequential and combinational elements separately: only the registers in the critical paths are touched by TDP (in practice they represent a small percentage of the total number of registers), and the shortening of clock tree wirelength can be obtained with limited variation in signal wirelength and placement density. The approach consists of two steps: (1) incremental register placement guided by a virtual clock tree to reduce clock wiring capacitance while preserving signal wirelength and density, and (2) incremental TDP to minimize the total negative slack. For the first step, we propose a novel technique that combines clock-net contraction and register clustering forces to reduce the clock wirelength. For the second step, we propose a novel Lagrangian Relaxation formulation that minimizes total negative slack for both setup and hold timing violations. To solve the formulation, we propose a TDP technique using a novel discrete search that employs a Euclidean distance to define a proper neighborhood. For the experimental evaluation of the proposed approach, we relied on the ICCAD 2014 TDP contest infrastructure and compared our results with the best results obtained from that contest in terms of timing closure, clock tree compactness, signal wirelength, and density. Assuming a long displacement constraint, our technique achieves worst and total negative slack reductions of around 24% and 26%, respectively. In addition, our approach leads to 44% shorter clock tree wirelength with negligible impact on signal wirelength and placement density. In the face of such results, the proposed coupling seems a useful approach to handle the challenges faced by contemporary physical synthesis.

The literature on scratchpad memories (SPMs) seems to indicate that the use of dynamic overlaying supersedes static, non-overlay-based (NOB) allocation. Although overlay-based (OVB) techniques operating at source-level code might benefit from multiple hot spots for higher energy savings, they cannot exploit libraries. When operating on binaries, OVB approaches lead to smaller savings, often require dedicated hardware, and sometimes prevent data allocation. Besides, all saving reports published so far ignore that, in cache-based systems, caches are likely to be optimized prior to SPM allocation. We show experimental evidence that, when handling binaries, NOB memory savings (15% to 33% on average) are as good as or better than OVB's. Since our savings (as opposed to related work) were measured after cache tuning -- when there is less room for optimization, our results encourage the use of simpler NOB methods to build library aware allocators that cannot depend on dedicated hardware. We also show that, given the capacity Ct of the equivalent pretuned cache, the optimal SPM size lies in [Ct/2, Ct] for 85% of the evaluated programs. Finally, we show counter-intuitive evidence that, even for cache-based architectures containing small SPMs, procedures should be preferred for allocation instead of basic blocks.

Binary tools are crucial to platform-based design, specially in early development of hardware-dependent software since it effectively enables hardware-software co-design. In this chapter we present the mechanisms available in ArchC that allows the automatic generation of binary tools such as assemblers, disassemblers, linkers, and debuggers. We start by describing the ArchC language extensions used to declare assembly language symbols, instruction syntax, instruction encoding, and operand modifiers. Following the language support, we show how our retargeting technique allows the automatic generation of the binary tools. We also discuss the GNU binutils framework and how it fits into our retargetability mechanism. We close the chapter by guiding the reader through the steps required to generate the tools from a processor model written in ArchC.

The main goal of this book is to enable Electronic System Level (ESL) research based on an open-source infrastructure. Two key components in this infrastructure are SystemC, as a hardware and system description language, and ArchC, as an architecture description language. In order to make it possible to readers that are not familiar with SystemC and/or ArchC to follow the model and platform descriptions presented in the remaining chapters of this book, this chapter briefly reviews the main concepts related to these two open-source languages. Moreover, ArchC will be put in practical use in the following chapters. Nevertheless, this chapter does not have the intention to be a complete specification or manual of these languages. Throughout the text, we point out references were a complete specification can be found.

Although SystemC is considered the most promising language for SoC functional modeling, it does not come with built-in power modeling capabilities. This chapter presents PowerSC, a power estimation framework which instruments SystemC for power characterization, modeling and estimation. Since it is entirely based on SystemC, PowerSC allows consistent power modeling from ESL to lower abstraction levels. Section 8.1 shows how SystemC is extended to handle power, Sect. 8.2 describes how to instrument SystemC descriptions for power estimation, Sect. 8.3 illustrates how PowerSC allows the user to perform estimations either at RTL or gate-level with the same instrumentation. Finally, Sect. 8.4 explains how to put PowerSC to work.

Systems-on-chip (SoCs) result from the evolution of VLSI technology and the growth of integrated circuit complexity. As it happens each time design complexity impairs the expected time-to-market, the quest for higher productivity involves abstraction, reuse, automation, and exploration. This chapter reviews how such notions are handled at the Electronic System Level (ESL). By discussing the requirements of an ESL representation and their impact on the design flow, the chapter shows how the open-source artifacts described in this book fit in the ESL landscape.

Since SoC design space exploration has to consider alternative target CPUs, retargetable tools are required. To comply with the promising TLM paradigm, designs usually start with untimed models and timing annotation is performed later. As a result, time-constraints are imposed to pre-compiled code. This paper describes a time-constraint-driven technique that harmonizes the pre-compiled code to the annotated constraints by performing automatically-retargetable assembly code scheduling, thereby avoiding full recompilation.

SoC design asks for tools to inspect embedded code and to pinpoint its bugs. Since design exploration may require that the code execute in distinct candidate processors, inspection tools must be retargeted. Besides, the time-to-market pressure makes automatic retargeting mandatory. This can be accomplished through tool generation from a formal model of each target processor, written in some architecture description language (ADL). This work extends a binary utility generator based upon the ArchC ADL by providing a technique for automatically retargeting disassemblers and debuggers. For experimental validation, we relied on the well-known MiBench and Dalton benchmarks. The results obtained from our retargeted tools and those from native tools were compared for distinct RISC and CISC architectures (i8051, MIPS, SPARC and PowerPC).