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FlexRay is a hybrid communication protocol tailored to the requirements in the automotive domain, supporting both time-triggered and event-triggered communication with high data-rates. The time-triggered static segment is commonly used for in-vehicle communication while the event-triggered dynamic segment is used for diagnostics and configuration. This paper addresses the problem of synthesizing schedules for the static FlexRay segment for asynchronous scheduling, following the design approach of current automotive architectures. Previous approaches largely focused on FlexRay 2.1 while the few existing approaches for FlexRay 3.0 are nonoptimal in several aspects. As a remedy, our framework makes use of all new features of version 3.0 while supporting the still predominantly used FlexRay 2.1, making it backward compatible. The following approaches are proposed: 1) a single-stage integer linear programming (ILP) approach that determines an optimal solution but does not scale; 2) a multistage ILP for combining previously generated subsystem schedules to a global schedule. It clearly improves the scalability but is not optimal. The multistage approach allows to integrate and convert existing FlexRay 2.1 schedules into a FlexRay 3.0 schedule which is important for legacy reasons, i.e., to reduce testing and certification efforts; 3) a greedy heuristic which scales well and obtains high quality solutions in comparison with the optimal solution, but is unsuitable to integrate existing schedules; and 4) metaheuristic approaches based on genetic algorithms or simulated annealing to evaluate the benefits of the proposed approaches. [ABSTRACT FROM AUTHOR]

Active balancing architectures effectively increase the efficiency of large battery packs by equalizing charge between cells. For this purpose, a balancing circuit and appropriate control scheme have to be designed to enable the charge transfer via energy storage elements such as inductors. Using a manual approach to design balancing architectures can be tedious and error-prone, resulting in potentially suboptimal solutions. As a remedy, this paper presents an automatic synthesis of balancing circuits and their corresponding control, optimizing the number of required metal-oxide-semiconductor field-effect transistors, and necessary control signals. The proposed synthesis combines a satisfiability solver to explore the search space with a graph-based verification that iteratively excludes infeasible solutions until the optimal architectures are obtained. The experimental results are carried out for three given template circuits and two signal templates. The synthesis results in architectures that are superior in terms of all design objectives in comparison to solutions from literature that result from a manual design approach. [ABSTRACT FROM PUBLISHER]

Active cell balancing is the process of equalizing the State-of-Charge (SoC) of all cells in a series-connected battery pack via charge transfers. While several balancing architectures and equalization strategies exist in the literature, optimization of the circuit components in a balancing architecture has not been sufficiently studied so far. Intuitively, one would select components with low parasitic resistances to minimize the energy dissipation. However, as will be shown in this paper, this might not be an optimal choice in most situations. In this paper, we propose an optimization framework that performs an efficient design space exploration to identify the energy-efficient circuit configuration of a balancing architecture. Moreover, for the first time, we propose a methodology to obtain the optimal operating frequency of an active cell balancing architecture and a control circuit to maintain the operation at the optimal frequency. For this purpose, we derive a closed-form analytical model of the charge transfer process with which we obtain the performance metrics required for our framework. Case studies show that such optimally dimensioned active cell balancing architectures operated at the optimal frequency reduce the energy dissipation by approximately 49% compared to the intuitive approach of selecting components with least parasitic resistances. [ABSTRACT FROM AUTHOR]

Due to the growing interconnectedness and complexity of in-vehicle networks, in addition to safety, security is becoming an increasingly important topic in the automotive domain. In this paper, we study techniques for detecting security infringements in automotive electrical and electronic (E/E) architectures. Toward this we propose in-vehicle network traffic monitoring to detect increased transmission rates of manipulated message streams. Attacks causing timing violations can disrupt safety-critical functions and have severe consequences. To reduce costs and prevent single points of failure, our approach enables an automatic distribution of detection tasks among selected E/E architecture components, such as a subset of electronic control units. First, we analyze a concrete E/E system architecture to determine the communication parameters and properties necessary for detecting security attacks. These are then used for a parametrization of the corresponding detection algorithms and the distribution of attack detection tasks. We use a lightweight message monitoring method and optimize the placement of detection tasks to ensure a full-coverage of the E/E system architecture and a timely detection of an attack. [ABSTRACT FROM PUBLISHER]

Modern vehicles employ a large amount of distributed computation and require the underlying communication scheme to provide high bandwidth and low latency. Existing communication protocols like Controller Area Network (CAN) and FlexRay do not provide the required bandwidth, paving the way for adoption of Ethernet as the next generation network backbone for in-vehicle systems. Ethernet would co-exist with safety-critical communication on legacy networks, providing a scalable platform for evolving vehicular systems. This requires a high-performance network gateway that can simultaneously handle high bandwidth, low latency, and isolation; features that are not achievable with traditional processor based gateway implementations. We present VEGa, a configurable vehicular Ethernet gateway architecture utilising a hybrid FPGA to closely couple software control on a processor with dedicated switching circuit on the reconfigurable fabric. The fabric implements isolated interface ports and an accelerated routing mechanism, which can be controlled and monitored from software. Further, reconfigurability enables the switching behaviour to be altered at run-time under software control, while the configurable architecture allows easy adaptation to different vehicular architectures using high-level parameter settings. We demonstrate the architecture on the Xilinx Zynq platform and evaluate the bandwidth, latency, and isolation using extensive tests in hardware. [ABSTRACT FROM AUTHOR]

Car manufacturers provide a growing variety of models and configuration options for customers. In the highly competitive and cost-driven automotive industry, managing these variants and increasing the reuse of functionality in different variants has therefore become one of the key challenges. This paper addresses the problem of generating variant schedules for time-triggered electrical/electronic-architectures. We propose a multischedule synthesis approach that determines the common parts of multiple variants and generates a schedule that exploits this commonality. Hence, a multischedule defines individual variant schedules with an identical schedule for applications common to different variants. This makes these applications variant-independent, thus, reduces the testing and integration efforts as it only has to be done once. Multischedule synthesis involves several challenges, viz., identification of commonality between different variants, schedule synthesis for common parts, and the integration of uncommon parts. Consequently, the schedule synthesis approach presented here is very different from conventional approaches. Finally, to address the increased complexity, we also propose a divide-and-conquer approach to partition the problem, improving the scalability. [ABSTRACT FROM AUTHOR]