100 results on '"Luo, Yandong"'
Search Results
2. Circumventing drug resistance in gastric cancer: A spatial multi-omics exploration of chemo and immuno-therapeutic response dynamics
3. Short-term effects of extreme meteorological factors on daily outpatient visits for anxiety in Suzhou, Anhui Province, China: a time series study
4. New Security Challenges on Machine Learning Inference Engine: Chip Cloning and Model Reverse Engineering
5. Multi-omics analysis reveals the chemoresistance mechanism of proliferating tissue-resident macrophages in PDAC via metabolic adaptation
6. Physarum Polycephalum Inspired Search Strategy for Multi-robot
7. H3D-Transformer: A Heterogeneous 3D (H3D) Computing Platform for Transformer Model Acceleration on Edge Devices
8. A FeFET-Based ADC Offset Robust Compute-In-Memory Architecture for Streaming Keyword Spotting (KWS)
9. Physarum Polycephalum Inspired Search Strategy for Multi-robot
10. Robot Chain Based Self-organizing Search Method of Swarm Robotics
11. Corrigendum to: “Circumventing drug resistance in gastric cancer: A spatial multi-omics exploration of chemo and immuno-therapeutic response dynamics” [Drug Resist Updates 74 (2024) 101080]
12. The relationship between perceived social support and the number of injuries among left-behind children in the Chaoshan region, China: The chain-mediating role of self-esteem and psychological resilience
13. 3-D Heterogeneous Integration of RRAM-Based Compute-In-Memory: Impact of Integration Parameters on Inference Accuracy
14. Developing Through-Wafer Via (TWV) and Plasma Dicing Process for Silicon Interconnect Fabric (Si-IF)
15. Short-term effects of extreme meteorological factors on daily outpatient visits for anxiety in Suzhou, Anhui Province, China: a time series study
16. Large Fragment InDels Reshape Genome Structure of Porcine Alveolar Macrophage 3D4/21 Cells
17. A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect
18. An Algorithm-Hardware Co-Design for Bayesian Neural Network Utilizing SOT-MRAM’s Inherent Stochasticity
19. Performance Benchmarking of Spin-Orbit Torque Magnetic RAM (SOT-MRAM) for Deep Neural Network (DNN) Accelerators
20. Robust Processing-In-Memory With Multibit ReRAM Using Hessian-Driven Mixed-Precision Computation
21. BEOL-Compatible Superlattice FEFET Analog Synapse With Improved Linearity and Symmetry of Weight Update
22. Accelerating On-Chip Training with Ferroelectric-Based Hybrid Precision Synapse
23. BEOL Compatible Superlattice FerroFET-based High Precision Analog Weight Cell with Superior Linearity and Symmetry
24. Monolithic 3D Compute-in-Memory Accelerator with BEOL Transistor based Reconfigurable Interconnect
25. Thermal Reliability Considerations of Resistive Synaptic Devices for 3D CIM System Performance
26. AILC: Accelerate On-Chip Incremental Learning With Compute-in-Memory Technology
27. RRAM for Compute-in-Memory: From Inference to Training
28. A Ferroelectric-Based Volatile/Non-Volatile Dual-Mode Buffer Memory for Deep Neural Network Accelerators.
29. A Runtime Reconfigurable Design of Compute-in-Memory–Based Hardware Accelerator for Deep Learning Inference
30. Swarm Robot Exploration Strategy for Path Formation Tasks Inspired by Physarum polycephalum
31. Fault diagnosis of industrial robot reducer by an extreme learning machine with a level-based learning swarm optimizer
32. Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning
33. First Experimental Demonstration of Robust HZO/β-Ga₂O₃ Ferroelectric Field-Effect Transistors as Synaptic Devices for Artificial Intelligence Applications in a High-Temperature Environment
34. A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator
35. A FeRAM based Volatile/Non-volatile Dual-mode Buffer Memory for Deep Neural Network Training
36. A Ferroelectric-based Volatile/Non-volatile Dual-mode Buffer Memory for Deep Neural Network Accelerators
37. (Invited) Ferroelectric Transistors for Synaptic Devices: Challenges and Prospects
38. Array-Level Programming of 3-Bit per Cell Resistive Memory and Its Application for Deep Neural Network Inference
39. A Variation Robust Inference Engine Based on STT-MRAM with Parallel Read-Out
40. Benchmark of the Compute-in-Memory-Based DNN Accelerator With Area Constraint
41. Accelerating Deep Neural Network In-Situ Training With Non-Volatile and Volatile Memory Based Hybrid Precision Synapses
42. Investigation of Read Disturb and Bipolar Read Scheme on Multilevel RRAM-Based Deep Learning Inference Engine
43. Toward target search approach of swarm robotics in limited communication environment based on robot chains with elimination mechanism
44. Impact of Read Disturb on Multilevel RRAM based Inference Engine: Experiments and Model Prediction
45. Design Impacts of Back-End-of-Line Line Edge Roughness
46. Benchmark Non-volatile and Volatile Memory Based Hybrid Precision Synapses for In-situ Deep Neural Network Training
47. Benchmark of Ferroelectric Transistor-Based Hybrid Precision Synapse for Neural Network Accelerator
48. DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies
49. Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning
50. Robot Chain Based Self-organizing Search Method of Swarm Robotics
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