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A central endeavour in bioelectronics is the development of logic elements to transduce and process ionic to electronic signals. Motivated by this challenge, we report fully monolithic, nanoscale logic elements featuring n- and p-type nanowires as electronic channels that are proton-gated by electron-beam patterned Nafion. We demonstrate inverter circuits with state-of-the-art ion-to-electron transduction performance giving DC gain exceeding 5 and frequency response up to 2 kHz. A key innovation facilitating the logic integration is a new electron-beam process for patterning Nafion with linewidths down to 125 nm. This process delivers feature sizes compatible with low voltage, fast switching elements. This expands the scope for Nafion as a versatile patternable high-proton-conductivity element for bioelectronics and other applications requiring nanoengineered protonic membranes and electrodes.

Molecular motor gliding motility assays based on myosin/actin or kinesin/microtubules are of interest for nanotechnology applications ranging from cargo-trafficking in lab-on-a-chip devices to novel biocomputation strategies. Prototype systems are typically monitored by expensive and bulky fluorescence microscopy systems and the development of integrated, direct electric detection of single filaments would strongly benefit applications and scale-up. We present estimates for the viability of such a detector by calculating the electrostatic potential change generated at a carbon nanotube transistor by a motile actin filament or microtubule under realistic gliding assay conditions. We combine this with detection limits based on previous state-of-the-art experiments using carbon nanotube transistors to detect catalysis by a bound lysozyme molecule and melting of a bound short-strand DNA molecule. Our results show that detection should be possible for both actin and microtubules using existing low ionic strength buffers given good device design, e.g., by raising the transistor slightly above the guiding channel floor. We perform studies as a function of buffer ionic strength, height of the transistor above the guiding channel floor, presence/absence of the casein surface passivation layer for microtubule assays and the linear charge density of the actin filaments/microtubules. We show that detection of microtubules is a more likely prospect given their smaller height of travel above the surface, higher negative charge density and the casein passivation, and may possibly be achieved with the nanoscale transistor sitting directly on the guiding channel floor., Comment: Submitted to New Journal of Physics

We introduce a fabrication method for gate-all-around nanowire field-effect transistors. Single nanowires were aligned perpendicular to underlying bottom gates using a resist-trench alignment technique. Top gates were then defined aligned to the bottom gates to form gate-all-around structures. This approach overcomes significant limitations in minimal obtainable gate length and gate-length control in previous horizontal wrap-gated nanowire transistors that arise because the gate is defined by wet etching. In the method presented here gate-length control is limited by the resolution of the electron-beam-lithography process. We demonstrate the versatility of our approach by fabricating a device with an independent bottom gate, top gate, and gate-all-around structure as well as a device with three independent gate-all-around structures with 300 nm, 200 nm, and 150 nm gate length. Our method enables us to achieve sub-threshold swings as low as 38 mV/dec at 77 K for a 150 nm gate length., Comment: Submitted to Nanotechnology

We report the development of nanowire field-effect transistors featuring an ultra-thin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally-coated nanowires, which we used to produce functional $\Omega$-gate and gate-all-around structures. These give sub-threshold swings as low as 140 mV/dec and on/off ratios exceeding $10^3$ at room temperature. For the gate-all-around structure, we developed a novel fabrication strategy that overcomes some of the limitations with previous lateral wrap-gate nanowire transistors. Finally, we show that parylene can be deposited over chemically-treated nanowire surfaces; a feature generally not possible with oxides produced by atomic layer deposition due to the surface `self-cleaning' effect. Our results highlight the potential for parylene as an alternative ultra-thin insulator in nanoscale electronic devices more broadly, with potential applications extending into nanobioelectronics due to parylene's well-established biocompatible properties.

We report an electron-beam based method for the nanoscale patterning of the poly(ethylene oxide)/LiClO$_{4}$ polymer electrolyte. We use the patterned polymer electrolyte as a high capacitance gate dielectric in single nanowire transistors and obtain subthreshold swings comparable to conventional metal/oxide wrap-gated nanowire transistors. Patterning eliminates gate/contact overlap which reduces parasitic effects and enables multiple, independently controllable gates. The method's simplicity broadens the scope for using polymer electrolyte gating in studies of nanowires and other nanoscale devices., Comment: 20 pages, 4 figures. Supplementary information available at Nano Letters or by contact with APM

Triethylsilylethynyl anthradithiophene (TESADT) holds considerable promise for organic transistor applications due to the high electrical mobilities attained by post-deposition crystallization using solvent vapour annealing. We have studied thermal annealing as an alternative route to post-deposition crystallization of TESADT films. Thermal annealing initially appears promising, producing mm-sized crystal domains, but poor electrical performance is obtained, which we attribute to a combination of crack formation and potentially also structural transition during the anneal process. We also find that illumination has a significant positive effect on crystallization, possibly due to an optically-induced enhancement in molecular mobility during annealing. This suggests further studies of how solvent exposure, heat, substrate surface properties and particularly light exposure influence the ordering kinetics of TESADT are warranted., Comment: In press for Journal of Organic Semiconductors

We have studied the efficacy of (NH4)2Sx surface passivation on the (311)A GaAs surface. We report XPS studies of simultaneously-grown (311)A and (100) heterostructures showing that the (NH4)2Sx solution removes surface oxide and sulfidizes both surfaces. Passivation is often characterized using photoluminescence measurements, we show that while (NH4)2Sx treatment gives a 40 - 60 x increase in photoluminescence intensity for the (100) surface, an increase of only 2 - 3 x is obtained for the (311)A surface. A corresponding lack of reproducible improvement in the gate hysteresis of (311)A heterostructure transistor devices made with the passivation treatment performed immediately prior to gate deposition is also found. We discuss possible reasons why sulfur passivation is ineffective for (311)A GaAs, and propose alternative strategies for passivation of this surface.

Gate instability/hysteresis in modulation-doped p-type AlGaAs/GaAs heterostructures impedes the development of nanoscale hole devices, which are of interest for topics from quantum computing to novel spin physics. We present an extended study conducted using custom-grown, matched modulation-doped n-type and p-type heterostructures, with/without insulated gates, aimed at understanding the origin of the hysteresis. We show the hysteresis is not due to the inherent `leakiness' of gates on p-type heterostructures, as commonly believed. Instead, hysteresis arises from a combination of GaAs surface-state trapping and charge migration in the doping layer. Our results provide insights into the physics of Si acceptors in AlGaAs/GaAs heterostructures, including widely-debated acceptor complexes such as Si-X. We propose methods for mitigating the gate hysteresis, including poisoning the modulation-doping layer with deep-trapping centers (e.g., by co-doping with transition metal species), and replacing the Schottky gates with degenerately-doped semiconductor gates to screen the conducting channel from GaAs surface-states., Comment: 15 pages, 11 figures; Accepted for Physical Review B