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Analog modeling is used to study the role played by the inherited salt-sediment architecture of a salt-bearing rifted margin, developed by minibasin downbuilding and margin-scale gliding, and then incorporated into a fold-and-thrust belt system influenced by surface processes. Inherited salt bodies localize contractional deformation at different scales and the salt-sediment architecture determines structural styles of fold-and-thrust belts. In our analog models, a large-transport thrust detached along allochthonous model salt (silicone polymer) accumulated in a former distal raft system. And the squeezing of salt walls, together with the tilting of minibasins, accounted for most of the shortening in a salt wall-minibasin province. Shortening and surface processes promote the extrusion and erosion of about 75% of the original model salt. The role played by salt tectonics during the contraction of salt-bearing rifted margins could be underestimated because of the low salt-sediment ratio found in fold-and-thrust belts. Our modeling results are compared with and assist in the interpretation of a section along the Northern Calcareous Alps.

Proton Sound Detectors (ProSDs) sense (at low latency, RMS) after 50 ms acquisition (77.56 Gy total dose deposition).

A 4-channel front-end electronics chip in 65 nm CMOS technology (ASD65 nm) for muon drift tube chambers at high background counting rates in the ATLAS detector at High-Luminosity LHC and in future high-energy collider experiments is presented. Each channel of the ASD65 nm chip is a mixed-signal processing circuit consisting of a Charge Sensitive Preamplifier (CSP), a two-stage shaper, and a timing discriminator. The CSP exhibits a peaking time of 11 ns and a sensitivity of 1.1 mV/fC. The peaking time of the full analog chain is 14.6 ns. The minimum signal-to-noise ratio of the channel is 15 dB for the minimum input charge of 5 fC, and it rises to 40.5 dB for the maximum input charge of 100 fC. At the output, the time representation of input signal is provided in both, CMOS level as well as low-voltage-differential-signal. Each channel consumes a current of 10.6 mA from a single 1.2 V supply, and occupies an area of 0.235 mm2. The specified performance parameters of the ASD65 nm have been achieved for 60 pF parasitic capacitance of the detector connected the input terminal.

IC-PIX28 (Integrated Circuit for PIXel detectors) is an analog read-out front-end fabricated in 28 nm Bulk-CMOS technology to process the charge signal produced by the pixel detector having 100 fF parasitic capacitance. The device is composed by a Charge Sensitive Pre-amplifier (CSPreamp) and a comparator. The development of IC-PIX28 manages several issues due to the poor analog performance of the standard-process MOS transistors in 28 nm Bulk-CMOS technology, whose choice is motivated by the expected rad-hard performance up to 1 Grad of Total Ionizing Dose. IC-PIX28 achieves performance robustness and low-power consumption by specific circuital solutions and it operates from a single 900 mV supply voltage. The full IC-PIX28 read-out channel consumes 4.3 μ W. The CSPreamp performs 35 mV/fC sensitivity, 40 dB Signal-to-Noise Ratio, and 0.033 fC (204 e rms − ) Equivalent Noise Charge. Moreover, a switched-capacitors inverter-based comparator performs the Time-over-Threshold (ToT, at very low power consumption) with a measured ToT range of 500 ns convertible in a digital word with a high bit resolution (> 14).

This paper presents a 4th-order continuous-time analog filter, with 100 MHz pass-bandwidth, based on the Super-Source-Follower biquadratic cell. The device is designed in order to meet specification for the latest telecommunications standards (LTE and 5G) and to efficiently operate in 16 nm-FinFET technology, exploiting the higher transistor intrinsic gain and efficiency, compared to the CMOS planar counterpart. Nonetheless, this work improves the Source-Follower analog filters state-of-the-art introducing a fully-differential biquadratic cell. The filter achieves 15.1 dBm in-band IIP3 at 10 MHz & 11 MHz input tones, with $968\ \mu \mathrm{W}$ power consumption from a single 1V supply voltage. In-band integrated noise is $85.78\ \mu \mathrm{V}_{\mathrm{rms}}$ for an overall Figure-of-Merit of 162.8 dB (j−1) which outperforms analog filters state of the art.

[EN] In the framework of the search for dark matter in the form of WIMPs using superheated liquids, a study is conducted to establish a computational procedure aimed at determining how the thermodynamic conditions kept inside a particle detector affect the acoustic signal produced by bubble nucleation. It is found that the acoustic energy injected into the liquid by the growing vapour bubble increases as the liquid pressure is decreased and the superheat degree is increased, the former effect being crucial for the generation of a well-intelligible signal. A good agreement is met between the results of the present study and some experimental data available in the literature for the amplitude of the acoustic signal. Additionally, the higher loudness of the alpha-decay events compared with those arising from neutron-induced nuclear recoils is described in terms of multiple nucleations., The authors are grateful to Walter Fulgione for the valuable discussions and suggestions and for his help in reviewing the manuscript.

The synergy between schematic and layout to optimize the performance of analog circuits in scaled technologies is addressed for the case of an innovative analog filter, developed in the 28nm node. This benchmark is a 75MHz 4th-order low-pass analog filter in 28nm-CMOS composed by two Active-RC Rauch biquadratic cells. The architecture is customized to properly operate in the challenging conditions of low V DD (0.9V) and low [V DD -V TH ] space (≈ 0.4V) and overcoming the poor analog performance of the 28nm MOS devices. In these directions, aggressive opamp input and output CMFB are applied. The paper shows how layout could corrupt the high-frequency performance of the filter without specific solutions. Optimized and synergic design and layout solutions are validated by the experimental results. The filter consumes 2.68mW from a single 0.9V-V DD . 11.5dB IIP3 at 20&21MHz and 40dBc of THD at 20MHz, respectively are achieved, while performing 310µV RMS of integrated in band noise.

This paper presents the design and the experimental validation of a 6th-order continuous-time low-pass filter in 28 nm bulk-CMOS, based on the cascade of 3 Rauch biquadratic cells. Each cell exploits a broad-bandwidth Operational Transconductance Amplifier (OTA), without Miller compensation scheme for differential Loop Gain stability. This maximizes the OTA unity gain bandwidth, with no power increase w.r.t classical compensation schemes, and improves both frequency response accuracy and linearity over the filter pass-band. This aggressive design choice is sustained by the higher 28 nm CMOS transistor’s transition frequency and by the intrinsic feature of the Rauch cell, whose R-C feedback/direct path nets introduce two poles and two zeros that self-compensate the differential loop-gain. On the other hand, the proposed OTA only exploits a compensation scheme for the common-mode signal stability, which does not affect the differential signal. The prototype synthesizes 50 MHz low-pass frequency response at 3.3 mA current consumption from a single 1.1 V supply and performs 18 dBm and 16.5 dBm Input IP3 for 10&11 MHz and 40&41 MHz input tones, equalizing the linearity performance over the filter pass-band, just thanks to the OTA wider bandwidth. This finally allows 153 dBJ-1 and 158 dBJ-1 Figure-of-Merit at 10&11 MHz and 40&41 MHz input tones.

This paper presents a Fast-Tracker front-end (FTfe) for ATLAS small-diameter Muon Drift Tube (sMDT) detectors of the Phase-II Upgrade HL-LHC. This design addresses the higher rate capability required by sMDT and reduced the dead-time below the maximum drift time, further increasing the efficiency. The front-end ensures a fast baseline restoration with a reset interval of maximum 160 ns, so that the secondary spurious pulses are avoided and the successive muon signals can be detected soon and correctly. The device has been designed in 1V-28nm-CMOS technology; outstanding 4.7mV/fC sensitivity and 0.24fC ENC are achieved with a core area of 0.03 mm2.

In order to fully exploit the physics potential of the ATLAS experiment at the HL-LHC, the trigger rate of and maximum latency of the first-level trigger system will be increased to 1 MHz and 10 μ s , respectively. In addition, a new first-level muon track trigger with high momentum resolution based on the ATLAS precision Muon Drift-Tube (MDT) chambers will be employed which requires triggerless readout. The TDC ASICs of the current front-end electronics of the MDT chambers are incompatible with these requirements. The front-end boards, each with a TDC chip and three 8-channel amplifier–shaper–discriminator (ASD) chips have to be replaced. Therefore, a new octal ASD2 ASIC has been developed in modern 130 nm IBM/Global Foundries CMOS technology. The chip also contains a Wilkinson ADC to perform both time-over-threshold and signal charge measurement. The ASD design has been fully qualified for the serial production of 80000 chips for ATLAS. The performance in terms of signal rise time and channel uniformity significantly surpasses the one of the previous chip while keeping the power consumption constant. In addition to the characterization with test pulses, several chips have been mounted on the front-end boards and tested in a muon beam at the Gamma Irradiation Facility GIF++ at CERN up to high counting rates where the superior drift time and spatial resolution becomes evident.

In this work we report on early-orogenic fracture patterns affecting a Cretaceous to Eocene sedimentary succession exposed in western Greece. These rocks belong to the Cenozoic External Hellenides, which form the western portion of the Aegean orocline. The analysis of fracture type, orientation, and crosscutting relationships provides constraints on the stress and strain patterns during the early stages of orocline formation. The fracture patterns in the study area includes early-orogenic extensional fractures arranged into two mutually orthogonal sets. These developed during progressive burial in the forebulge-foredeep system, ahead of the advancing compressive front. Tectonic solution seams at a high angle to bedding postdate these extensional structures. Solution seams are arranged in different sets, oblique to each other, and developed in the early stages of thrusting and folding. Extensional structures and solution seams are oblique to each other. Their orientation and crosscutting relationships provide evidence for clockwise vertical axis rotation of stress directions with time. This is consistent with the progressive arching of the forebulge-thrust belt system during progressive slab retreat.

This paper presents a Real-Time Neural Spikes (RT-Neu) Imaging system on FPGA that processes and detects the electrical activity of a neurons population taken from rat hippocampi on an Electrolyte-Oxide-Semiconductor (EOS) Multi Electrode Array (MEA) local matrix of 32×32 pixels. RT-Neu has been implemented on Xilinx Zynq-7000 ARM/FPGA SoC. It receives the neural signals coming from a 9.375 kSample/(sec·pixel) 32×32 pixels EOS Biosensor, filters the single-pixel low-frequency offset/noise components and finally performs a multi-pixel signal processing (using a PCA-based correlation algorithm) to provide a final spatial map of the neural culture electrical activity. The correlation algorithm has been implemented to operate on multiplexed signals allowing to identify single neural Action Potentials (AP) with amplitudes as low as 215 μV 0-PEAK . A dedicated GUI has been developed to monitor in real-time the neuron population electrical activity and whose demo video can be found at [1].

This paper presents an FPGA implementation of a DSP performing real time spike detection on the electrical activity of an in vitro neuronal culture of rat hippocampi. The DSP enhances the Signal-to-noise ratio (SNR) of samples recorded by a 1024 pixels Multi Transistor Array (MTA) at 9375 Samples/Sec per pixel of $\sim 6\ \boldsymbol{\mu}\mathbf{m}$ pitch. The implementation integrates in the same system a Time Division Multiplexing (TDM) filter and a spatio-temporal correlation algorithm, to increase the SNR up to identify spikes as low as $215\ \boldsymbol{\mu}\mathbf{V}_{0-\mathbf{PEAK}}$ . The digital filter is a 2nd order high pass Infinite input response (IIR) Chebyshev filter. The spatio-temporal correlation exploits the MTA smaller pixels size and the high sample-rate to compute an equivalent pixel from a group of 7 pixels and 3 consecutive frames for a total of 21 samples and it is supported by a multi-channel noise power estimation. Finally, this paper shows the results achieved on the performed experiments and compares the system with others experiments using different sensors and algorithms.

A Fast Tracker analog front end for small-diameter Muon Drift Tube (sMDT) detectors is hereby presented. The analog channel has been integrated in 28 nm CMOS technology and significantly improves state-of-the-art sMDT read-out systems thanks to a novel signal processing technique exploited to extract information from sMDT detectors speeding-up the processing time and to limit fake events detection. The main idea is to implement a fast reset of all continuous-time analog stages that occurs just after the charge (i.e. event) detection. This has two main advantages for sMDT read-out: fast processing and negligible signal corruption due to non-relevant pile-up signals. Nonetheless, the realization in 28nm bulk-CMOS technology implies challenges for analog design but advantages in terms of speed, area occupancy and radiation hardness. The proposed analog channel occupies 0.03 mm2 and consumes 1.9 mW from 1 V supply voltage.

This paper presents the development of an Internet-of-Things (IoT) Cooperative System (IoT-CS) based on local Event-Driven response. After introducing IoT basic concepts and most common computational schemes (with particular attention on the differences between Cloud, Fog, and Cooperative computing paradigms), an innovative scheme for IoT will be presented. Thanks to the introduction and development of several intermediate layers between the sensor network and the Cloud, the hereby proposed system allows overcoming most of the problems of the state-of-the-art paradigms. In order to validate the proposed solution the most relevant aspects of this implementations will be presented.

This paper presents the result of a multidisciplinary experiment where electrical activity from a cultured rat hippocampi neuronal population is detected in real time by a FPGA implemented digital circuit. State-of-the-art EOMOSFET Multi Electrode Array (MEA) biosensors exploits a capacitive coupling between the biological environment and the sensing electronics to minimize invasiveness and cell damage, at the price of a lower SNR. For this reason, they are typically improved by noise rejection algorithms. Real time neural spikes detection opens unthinkable scenarios, allowing to stimulate single neurons in response to their behavior, possibly improving medical conditions like epilepsy. In this scenario, a spike sorting algorithm has been hardware implemented, allowing real time neural spike detection with a latency of 165ns.

This paper presents the design in 28nm-CMOS technology of a 100MHz–3dB-bandwidth analog filter based on the Flipped-Source-Follower stage. The filter performs large inband linearity thanks to a proper local loop, whose optimization at design level can be shielded from the Source-Follower input transistor that dominates the noise power. This enables better noise/linearity trade-off vs. power efficiency comparing with the Source-Follower filters state-of-the-art. The circuit implements a 4th-order Butterworth low-pass transfer function and achieves 12.5dBm IIP3 at 968µW power consumption from a single 1V supply voltage. The in-band noise power spectral density is 8nV/√Hz resulting in an in-band integrated noise of 98µVRMS. Total Harmonic Distortion at 20 MHz is −40dB with −6dBm single tone output signal, resulting in 64dB Dynamic Range. The achieved Figure-of-Merit (160.5 J−1) compares very favorably with the state-of-the-art.

Resumen La ansiedad es parte de un proceso normal de adaptacion al ambiente, que en algunas circunstancias puede llegar a intensidad y duracion excesivas, afectando la funcionalidad del individuo. Consiste en una serie de sintomas psiquicos y somaticos que pueden ser reactivos a un acontecimiento estresante o enmarcarse en el contexto de una patologia. Diferentes enfermedades medicas y el uso de sustancias pueden presentarse con sintomatologia ansiosa, por lo cual es indispensable una correcta anamnesis y un examen medico, asi como la realizacion de las pruebas complementarias necesarias. Hay que tener en cuenta los criterios diagnosticos de diferentes trastornos psiquiatricos, tanto los trastornos de ansiedad como otros trastornos que pueden cursar con ansiedad aguda. El trastorno de panico es el prototipo de ansiedad aguda. El tratamiento es esencialmente psicologico y farmacologico (benzodiacepinas, con otras opciones segun la clinica).

This paper presents the results of a multidisciplinary experiment where the electrical activity of a rat hippocampus cultured neurons population has been detected and mapped by an advanced FPGA spike-sorting algorithm. Neurons are growth over a silicon chip that is thus capacitively coupled with neuronal cells. Due to noise power coming from bio-silicon interface and analog electronics signal processing, the Action Potentials detection intrinsically needs advanced noise rejection algorithms which are often software/off-line implemented. This approach disables instantaneous detection of neural spikes and cannot be obviously used for real-time electrical stimulation. In this scenario, this paper presents a proper FPGA system able to separate relevant neuronal cells potentials from noise. The FPGA output signals provide real time spatial mapping of biosensor electrical activity, noise and synchronous neural network activity.

In this paper a 600MHz 4th order low-pass analog filter in CMOS-28nm is presented. The transfer function is obtained with the cascade of two Active-RC Rauch biquadratic cells. Each cell is based on a novel OPAMP optimized for very high frequency operation achieving a Unity Gain Bandwidth (UGBW) > 7GHz. The developed three stage folded OPAMP exploits a feed-forward compensation technique to maximize bandwidth and an improved Common Mode Feedback Circuit (CMFB) necessary to reduce parasitic poles and to guarantee acceptable CMFB phase margin. The OPAMP is able to manage the very low V DD /V TH ratio of the 28nm process lowering its input common mode voltage in respect with input and output common mode voltage of the whole filter. The prototype consumes 11.4mW from a single 0.9V supply voltage, achieving 600MHz of bandwidth with an in-band integrated noise of 750μV RMS . The IIP3 calculated at 400 and 450MHz is 12.5dBm.

In this paper a 75MHz 4th order low-pass analog filter in CMOS-28nm is presented. The filter is composed by the cascade of two Active-RC Rauch biquadratic cells. The hereby proposed design manages a very low Vdd/Vth ratio (

The Total Ionizing Dose (TID) levels foreseen after the future upgrade of the CERN Large Hadron Collider (High Luminosity LHC) will heavily influence the performance of the electronics. A TID level of 1GigaRad will be accumulated in the innermost layer of the pixel detector in 10 years of operations, which could damage the readout circuits behavior with important failures in the experiments. To prevent this situation, the choice of a proper technology for the readout ASICs represents a key point. This paper deals with the characterization of single transistors and of an analog circuit, both realized in a TSMC 28nm bulk CMOS technology, after being irradiated with 1 GigaRad TID. nMOS devices result more resistant than pMOS showing a weak degradation of the electrical parameters. Nevertheless, the considerable leakage current increment is not negligible because it could affect analog circuits as that hereby presented. In the proposed analog circuit, the high radiation level induces a 20% gain reduction and an 80% slowdown of the Charge Sensitive Preamplifier time response.

This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (

A 28 nm CMOS-bulk lowpass analogue filter architecture is hereby proposed. The filter is based on an improved Active-Gm -RC structure, where both poles of a Miller-compensated operational amplifier (OPAMP) have been used for synthesising a third-order filter. Several well-known issues related to the 28 nm process node have been hereby mitigated by proper circuit/design techniques, enabling large signal-to-noise ratio (SNR) and 13.5 dBm IIP3. The proposed circuital solution performs 59 dB-SNR at 340 µW power consumption from a single 0.9 V supply-voltage. This allows one of the higher figure-of-merit (156 dB) in sub-1 V analogue filters state of the art.

The complete design and electrical characterization of a readout frontend for high luminosity pixel detectors is hereby presented. The design has been carried out in 28nm bulk-CMOS technology. The selected technology process shows significant advantages in terms of radiation hardness, faster/low-power digital signal processing and whole chip area reduction. Nonetheless, it is challenging in terms of operating point (0.9V supply voltage at 0.5V threshold voltage for standard process transistors), dynamic range, and large sensitivity to Process-Voltage-Temperature variations. The proposed integrated circuit includes the cascade of a low-noise preamplifier stage and a switched-capacitor inverter-based comparator. The overall system detects input charges up to 14fC and provides information about the amount of the charge with a Time-over-Threshold (ToT) technique. It features 4.3μW power consumption, 54dB Signal Noise Ratio and 0.02mm2 area occupancy. A ToT range of 180ns in 28nm bulk-CMOS represents a challenge for the future Time-to-Digital Converters (TDC) used in High-Energy-Physics readout systems. Analog front-end and TDC development anticipate a higher charge quantization resolution in the next physics experiments.

A 4th-order single-loop Follow-the-Leader-Feedback (FLFB) low-pass filter is hereby presented. The outstanding FLFB noise behavior has been exploited to release a specific power budget for linearity performance enhancement. Moreover, two pairs of complex poles are synthesized by using a single compact Active-RC cell, avoiding cascade of two or more stages (typically needed for high order filters), and relaxing this way noise power constraints. A prototype of the filter has been integrated in CMOS 0.18μm technological node, having 22.5MHz -3dB low-pass frequency. 21.5dBm in-band IIP3 and 76μVRMS input referred in-band integrated noise have been achieved. The SNR for a -40dB-THD is 69dB. The power consumption is 7mA. The efficiency of the hereby proposed technique is demonstrated by the very high Figure-of-Merit (160J-1) achieved by the FLFB filter comparing with the Active-RC filters state-of-the-art.

Impact of KIR/HLA genetic combinations on double umbilical cord blood transplantation outcomes. Results of a French multicentric retrospective study on behalf of the Societe Francophone de Greffe de Moelle et de Therapie Cellulaire (SFGM-TC) and the Societe Francophone d’Histocompatibilite et d’Immunogenetique (SFHI)

A 4th-order 28.8MHz low-pass analog filter uses a modified version of Sallen-Key (SK) biquad that solves the standard SK cell critical aspect due to the out-of-band zeros (OoB). The proposed cell completely cancel the OoB zeros by means of a low-power auxiliary path and a specific design optimization.

International audience; Graft failure remains a severe complication of hematopoietic stem cell transplantation (HSCT). Several risk factors have already beenpublished. In this study, we re-evaluated them in a large cohort who had the benefit of the recent experience in HSCT (2006–2012).Data from 4684 unrelated donor HSCT from 2006 to 2012 were retrospectively collected from centers belonging to the FrenchSociety for Stem Cell Transplantation. Among the 2716 patients for whom HLA typing was available, 103 did not engraft leading toa low rate of no engraftment at 3.8%. In univariate analysis, only type of disease and status of disease at transplant for malignantdiseases remained significant risk factors (P = 0.04 and Po0.0001, respectively). In multivariate analysis, only status of disease was asignificant risk factor (Po0.0001). Among the 61 patients who did not engraft and who were mismatched for 1 HLA class I and/orHLA-DP, 5 donor-specific antibodies (DSAs) were detected but only 1 was clearly involved in graft failure, for the others their rolewas more questionable. Second HSCT exhibited a protective although not statistically significant effect on OS (hazard ratio = 0.57[0.32–1.02]). In conclusion, only one parameter (disease status before graft) remains risk factor for graft failure in this recent cohort.

In this brief, a 28.8-MHz −3-dB frequency low-pass analog filter is presented. The filter synthesizes a fourth-order Butterworth transfer function, exploiting the well-known Sallen-Key (SK) biquadratic cell. The out-of-band zeros typically present in SK implementations are hereby completely canceled by using a low-power auxiliary path. This leads to a significant improvement of the stop-band rejection, at the cost of a small power for the same auxiliary path biasing. The design exhibits very large in-band IIP3 over the entire filter bandwidth (20 dBm at 10 MHz and 11 MHz), at 3.2-mW power consumption. The filter prototype has been designed in CMOS 0.18-μm technolog- ical node. The total area occupancy is 0.12 mm 2 and the in-band integrated noise is 101 μV RMS .

A 4th-order single-loop follow-the-leader-feedback (FLFB) low-pass continuous-time filter in CMOS 0.18 μm is hereby presented. The outstanding FLFB noise behaviour is exploited to allocate the power consumption to linearity performance. The low-pass filter prototype features 22.5 MHz-3 dB frequency, 21.5 dBm-IIP3 and 76 μVRMS input referred in-band integrated noise. The overall power consumption is 7 mA from a 1.8 V supply voltage. The signal-to-noise ratio for a -40 dB-total harmonic distortion is 69 dB.

Power consumption of high-speed low-resolution ADCs can be reduced by means of calibration. However, this solution presents some drawbacks like allocating a calibration time, calibration algorithm complexity, calibration circuit implementation, etc. In alternative, this paper presents a 5-bit 1Gs/s ADC without calibration, realized in a 90nm-CMOS. The device is based on the use of an improved version of double tail dynamic comparators, operating with a fixed bias current. These comparators present a reduced kickback noise, allowing increasing the input transistors sizes in order to improve the matching. The ADC current consumption is equal to 6.9mA from a 1.2V supply.

To evaluate the diagnostic performance of ultrasonography using second-generation contrast agent in the study of patients with focal prostate lesions and increased serum prostate-specific antigen (PSA) level.SIX CONSECUTIVE PATIENTS (AGE RANGE: 72-87 years) with increased PSA (≥4 ng/ml) underwent transrectal ultrasonography (TRUS) followed by contrast-enhanced ultrasonography (CEUS) with injection of second-generation contrast agent. All patients showed areas of abnormal echostructure suspicious for neoplastic lesions. On the basis of CEUS, a time/intensity curve of the suspected area was compared to that of a normal-appearing distant area of the gland and to the results of biopsy of the hypoechoic area.AT CEUS TWO DIFFERENT PATTERNS OF ENHANCEMENT WERE IDENTIFIED AND CONSIDERED TO BE SIGNIFICANT: pattern 1 characterized by a rapid rise in the time/intensity curve of the suspected area compared with the normal gland. Two out of six patients had this pattern and biopsy showed cancer in the biopsied area. Pattern 2 was characterized by a similar rise in the time/intensity curve of the suspected area compared with the normal gland. Four out of six patients had this pattern and biopsy showed prostatitis in the biopsied area.CEUS using second-generation contrast agent can on the basis of time/intensity curves show differences in vascularization in normal and pathological tissue. Evaluation of the two patterns seems to be useful for identifying areas requiring biopsy, particularly when peripheral hypoechoic areas are observed at TRUS. Our data need to be confirmed in a larger patient population.Sommario SCOPO: Determinare la performance diagnostica dell'ecografia con mezzo di contrasto di seconda generazione nello studio delle lesioni focali della prostata nei pazienti con elevati valori sierologici di antigene prostatico specifico. MATERIALI E METODI: Sei pazienti consecutivi (età 72–87 anni) con elevati valori di antigene prostatico specifico (≥4 ng/ml) sono stati sottoposti a ecografia transrettale tradizionale seguita da ecografia con mezzo di contrasto. In ogni paziente sono state identificate le aree periferiche di alterata ecostruttura sospette per lesione neoplastica. Queste aree sono state valutate con ecografia con mezzo di contrasto mediante curve di intensità/tempo. I dati ottenuti sono stati confrontati con la biopsia dell'area sospetta. RISULTATI: L'ecografia con mezzo di contrasto ha consentito di identificare due pattern distinti: pattern 1 caratterizzato da rapida elevazione della curva calcolata a livello della lesione rispetto all'intensità di impregnazione del parenchima adiacente. Due dei sei pazienti con questo pattern hanno dimostrato presenza di lesione neoplastica nell'area sottoposta a biopsia. Pattern 2 caratterizzato da scarsa elevazione della curva rispetto all'intensità dell'impregnazione del parenchima adiacente. I rimanenti 4 dei 6 pazienti esaminati avevano questo pattern e l'area bioptizzata ha dimostrato assenza di lesione neoplastica. CONCLUSIONI: L'ecografia con mezzo di contrasto di seconda generazione, attraverso le curve di intensità/tempo può identificare differenze di comportamento tra tessuto normale e patologico. Queste caratteristiche possono risultare utili soprattutto nel caso di aree ipoecogene all'ecografia basale per identificare le aree da sottoporre a biopsia.

This paper presents a chopper instrumentation amplifier designed in 28nm CMOS technology. The operational amplifier has a rail-to-rail folded cascode input stage, which ensures a constant gm over the available common-mode range. It is characterized by a Nested Miller compensation. All transistors operate in sub-threshold region; thus the opamp has been designed through a specific procedure for sub-threshold operation. The chopper technique is exploited to reduce the input referred offset and noise. The circuit operates with 0.9 V supply voltage and exhibits a simulated 106dB DC gain and 329kHz GBW. Montecarlo simulations demonstrate an offset distribution with 2.2μV standard deviation. The input noise spectral density is equal to 27nV/√Hz, giving a noise efficiency factor of 8.

An Integrated Chip prototype for PIXel read-out, named IC-PIX28 and designed in 28nm CMOS technology, is here presented. The chip features a single channel including a cascade of a Charge-Sensitive-Amplifier (CSA) and a comparator, performing a Time-over-Threshold (ToT) operation. The IC-PIX28 comparator can operate with thresholds ≥3mV, generated on-chip starting from an off-chip reference voltage. A few number of transistors allows processing an input charge within 0.1fC÷5fC range. With the minimum input charge, the CSA output peak voltage is 4.6mV reached in 11ns. In this condition, 44mV/fC sensitivity and 0.029fC (180e-) Equivalent-Noise-Charge (ENC) are achieved with 4.67μA current consumption and 0.07mm2 area occupancy.

The Phase-II Upgrade of the ATLAS Muon Detector requires new electronics for the readout of the MDT drift tubes. The first processing stage, the Amplifier-Shaper-Discriminator (ASD), determines the performance of the readout for crucial parameters like time resolution, gain uniformity, efficiency and noise rejection. An 8-channel ASD chip, using the IBM 130 nm CMOS 8RF-DM technology, has been designed, produced and tested. The area of the chip is 2.2 x 2.9 square mm size. We present results of detailed measurements as well as a comparision with simulation results of the chip behaviour at three different levels of detail. The Phase-II Upgrade of the ATLAS Muon Detector requires new electronics for the readout of the MDT drift tubes. The first processing stage, the Amplifier-Shaper-Discriminator (ASD), determines the performance of the readout for crucial parameters like time resolution, gain uniformity, efficiency and noise rejection. An 8-channel ASD chip, using the IBM 130 nm CMOS 8RF-DM technology, has been designed, produced and tested. The area of the chip is 2.2 × 2.9 square mm size. We present results of detailed measurements as well as a comparision with simulation results of the chip behaviour at three different levels of detail. The Phase-II Upgrade of the ATLAS Muon Detector requires new electronics for the readout of the MDT drift tubes. The first processing stage, the Amplifier-Shaper-Discriminator (ASD), determines the performance of the readout for crucial parameters like time resolution, gain uniformity, efficiency and noise rejection. An 8-channel ASD chip, using the IBM 130 nm CMOS 8RF-DM technology, has been designed, produced and tested. The area of the chip is 2.2 x 2.9 square mm size. We present results of detailed measurements as well as a comparision with simulation results of the chip behaviour at three different levels of detail.

In this paper a 4th-order 30MHz Butterworth low-pass analog filter is presented, exploiting the Sallen-Key (SK) biquadratic cell circuit. The out-of-band zeros typically present in SK cells, are cancelled by using a low-power auxiliary path, resulting in a significant improvement of the stopband rejection, at the cost of a small power budget for the same auxiliary path biasing. An efficient unity gain buffer has been used, based on super-source-follower stage, providing very large in-band IIP3 over the entire filter bandwidth (21.5dBm for 25MHz&26MHz input tones), at 3.2mW power consumption from a single 1.8V supply voltage. The filter prototype has been designed in CMOS 0.18μm tech. The total area occupancy is 0.12mm2, the in-band integrated noise is 197μVRMS.

Il testo introduce alla lettura dei saggi raccolti nel volume, che costituisce l'esito della prima parte della ricerca FIRB Living Urban Scape (LUS), condotta da un gruppo di ricerca che coinvolge Università IUAV di Venezia, UNiversità Roma Tre, Università di Trieste.

A low-power front-end for a capacitive MEMS accelerometer sensor is presented. The read-out front-end includes the analog preamplifier (to sense the signal coming from the MEMS) and a Successive-Approximation A/D Converter. The off-chip MEMS is a capacitive accelerometer. Constant-charge Capacitance-to-Voltage conversion has been used with a programmable-gain (to accommodate different MEMS sensor sensitivity) Continuous-Time Preamplifier to reduce power consumption and circuit complexity. A very high- impedance MOS transistor is used for MEMS biasing, thus providing a very low frequency (

GEMINI is a readout ASIC dedicated to the Triple-GEM detector. Fabricated in CMOS 180 nm technology, GEMINI pushes towards the state-of-the-art for this peculiar detector front-end, as regards the count rate and detector pixel parasitic capacitance sustainability. It features 16 channels, each one including a charge-sensitive preamplifier, an event discriminator with channel-independent threshold and an event-triggered reset. An embedded automatic calibration unit compensates performance for environmental, CMOS process and supply voltage variations. GEMINI sustains a 5Mcps count rate, managing up to 40 pF GEM detector capacitance and consuming 2.7mW/ch.

This paper presents GEMINI, an entire read-out System-on-Chip (SoC) to be used with the Triple Gas-Electron Multiplier (GEM) detector. Designed in CMOS 180 nm technology, GEMINI pushes towards the state-of-the-art for this peculiar detector front-end, as regards the count rate and detector pixel parasitic capacitance sustainability. It is composed of 16 channels, each performing a charge-to-voltage conversion via a Charge-Sensitive Preamplifier (CSP), a successive event discrimination with channel-independent threshold and an event-triggered reset. The CSP analog output and the LVDS discriminator output are available as chip outputs for each channel. The Q-to-V conversion accuracy is guaranteed by an automatic on-chip calibration unit, compensating for environmental, CMOS process and supply voltage variations. GEMINI is able to sustain a 5 Mcps count rate, managing up to 40 pF pixel capacitance and with a 2.7mW/ch power consumption.

International audience; We retrospectively analyzed the impact of HLA-DPB1 mismatches in a large cohort of 1342 French patients who underwent 10/10 HLA-matched unrelated HSCT. A significant impact of HLA-DPB1 allelic mismatches (2 vs 0) was observed in severe acute GVHD (aGVHDIII-IV) (risk ratio (RR)=1.73, confidence interval (CI) 95% 1.09-2.73, P=0.019) without impact on OS, TRM, relapse and chronic GVHD (cGVHD). According to the T-cell epitope 3 (TCE3)/TCE4 HLA-DPB1 disparity algorithm, 37.6% and 58.4% pairs had nonpermissive HLA-DPB1, respectively. TCE3 and TCE4 disparities had no statistical impact on OS, TRM, relapse, aGVHD and cGVHD. When TCE3/TCE4 disparities were analyzed in the graft-vs-host or host-vs-graft (HVG) direction, only a significant impact of TCE4 nonpermissive disparities in the HVG direction was observed on relapse (RR=1.34, CI 95% 1.00-1.80, P=0.048). In conclusion, this French retrospective study shows an adverse prognosis of HLA-DPB1 mismatches (2 vs 0) on severe aGVHD and of nonpermissive TCE4 HVG disparities on relapse after HLA-matched 10/10 unrelated HSCT.Bone Marrow Transplantation advance online publication, 3 November 2014; doi:10.1038/bmt.2014.253.