288 results on '"M. Athanas"'
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2. Domain-Specific Modeling and Optimization for Graph Processing on FPGAs.
3. Exploring FPGA-specific Optimizations for Irregular OpenCL Applications.
4. An effective probability distribution SAT solver on reconfigurable hardware.
5. Incorporating rapid design assembly into a virtual prototyping environment.
6. A q-gram birthmarking approach to predicting reusable hardware.
7. Inferring custom architectures from OpenCL.
8. Discovering Reusable Hardware Using Birthmarking Techniques.
9. FPGA-based accelerator development for non-engineers.
10. A device-agnostic tool for precomputing legal placements in modular design flows.
11. A power-efficient FPGA-based self-adaptive software defined radio.
12. Physical Layer for Spectrum-Aware Reconfigurable OFDM on an FPGA.
13. Architecturally-Enforced InfoSec in a General-Purpose Self-Configurable System.
14. Design Productivity for Configurable Computing.
15. High-Level Specification of Runtime Reconfigurable Designs.
16. A Sandbox for Exploring the OpenFire Processor.
17. Collaborative Signal Reinforcement in Sensor Networks.
18. Collaborative Synchronization for Signal Reinforcement in Sensor Networks.
19. Wires On Demand: Run-Time Communication Synthesis for Reconfigurable Computing.
20. Application of Self-Configurability for Autonomous, Highly-Localized Self-Regulation.
21. Exploring Non-Traditional Hardware-Software Interaction.
22. An 8-GHz Ultra Wideband Transceiver Prototyping Testbed.
23. A Key Management Architecture for Securing Off-Chip Data Transfers.
24. JHDLBits: The Merging of Two Worlds.
25. A design assembly framework for FPGA back-end acceleration.
26. A Versatile Framework for FPGA Field Updates: An Application of Partial Self-Reconfiguation.
27. On the Implementation of a Quasi-Generic Synchronization Architecture for Linear Digital Modulations.
28. RapidRadio: A Domain-Specific Productivity Enhancing Framework.
29. Towards Active Hardware.
30. A stream-based reconfigurable router prototype.
31. Cognitive Radio and Networking Research at Virginia Tech.
32. A Configurable Computing Approach Towards Real-Time Target Tracking.
33. A Run-Time Reconfigurable Engine for Image Interpolation.
34. A Stream-Based Configurable Computing Radio Testbed.
35. Dynamic Hardware Development.
36. Computing kernels implemented with a wormhole RTR CCM.
37. Stream synthesis for a wormhole run-time reconfigurable platform.
38. Wormhole Run-Time Reconfiguration.
39. Scheduling and partitioning ANSI-C programs onto multi-FPGA CCM architectures.
40. Using rapid prototyping to teach the design of complete computing solutions.
41. Quantitative analysis of floating point arithmetic on FPGA based custom computing machines.
42. High-Speed Region Detection and Labeling Using an FPGA Based Custom Computing Platform.
43. Implementation of a 2-D Fast Fourier Transform on an FPGA-Based Custom Computing Machine.
44. Incremental Design Methodology for Multimillion-gate Fpgas.
45. Image Processing on a Custom Computing Platform.
46. Context Switching in a Run-Time Reconfigurable System.
47. 10281 Summary - Dynamically Reconfigurable Architectures.
48. 10281 Abstracts Collection - Dynamically Reconfigurable Architectures.
49. Distributed hidden Markov model training on loosely-coupled multiprocessor networks.
50. Amstrong II: A Loosely Coupled Multiprocessor with a Reconfigurable Communications Architecture.
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