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Your search keyword '"M. Ishwarya Niranjana"' showing total 11 results
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11. Efficient high throughput decoding architecture for non-binary LDPC codes

Author

C Arul Murugan, B. Banuselvasaraswathy, M Ishwarya Niranjana, and K. Gayathree

Subjects
Environmental Engineering, Computer science, General Chemical Engineering, General Engineering, Binary number, Data_CODINGANDINFORMATIONTHEORY, Parallel computing, Hardware and Architecture, Computer Science (miscellaneous), Low-density parity-check code, Architecture, Throughput (business), Decoding methods, Biotechnology
Abstract

This article, deals with efficient trellis inbuilt decoding architecture for non-binary Linear Density Parity Check (LDPC) codes. In this decoder, a bidirectional recursion is embedded to enhance the layered scheduling and decoding latency, which in turn is used to minimize the number of iterations compared to existing techniques. Consequently, it is necessary to increase the throughput for improving the efficiency of the system. In addition, a compression technique is implemented for reducing the requirements of memory and the area. Trellis based decoder was used to reinforce the check node processing. The proposed decoder for LDPC codes yields high throughput when compared to other similar decoders presented in preceding works. The designed architecture was implemented using Cadence Virtuoso software. This decoder provides a throughput of about 39.21 Mb/s at clock frequency of 190MHz.

Published
2018
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