Search

Cu-In fine pitch interconnects are a viable approach for low temperature bonding technologies in 2.5 D and 3D integration. The unique metallurgical phenomena regarding the phase formation and growth of intermetallic compounds (IMCs) in the Cu-In system affect both processing conditions and the resulting interconnection properties. In this work, we investigate the formation Cu-In joints below 150 °C, i.e. in the solid state, under ambient conditions. Dies with Cu interconnects and In caps (25 µm diameter, 55 µm pitch) were bonded in a flip-chip process at moderate pressures and subsequently investigated by means of mechanical testing, cross-sectioning and microstructural analysis. In particular, we reveal the presence of stable interconnects exhibiting a ductile bonding zone. The resulting die shear strengths are in the range of 15-20 MPa.

The copper electrochemical deposition (Cu-ECD) filling capability of high aspect ratio through silicon vias (HAR-TSVs) and homogeneity over 300 mm wafers were investigated on a film stack of thermal ALD (thALD) TaxNy barrier with thermal ALD Ru seed in comparison to TixNy barrier with a standard Cu i-PVD seed layer using a commercial 300 mm plating tool. As a first step, Cu-ECD was conducted on wafers with TSV blind holes with aspect ratios (AR) of 10 to 12. To achieve this, a thermal ALD film stack of approximately 6 nm TaxNy and 9 nm Ru (with a sheet resistance of [25.6 ± 1.4] Ω/ϒ) were deposited at 250 °C. The reactants for the barrier layer were (tert-butylimido)tris(diethylamino)tantalum(V) (TBTDET) and ammonia (NH3) as co-reactant. For the Ru seed layer deposition (ethylcyclopentadienyl)(pyrrolyl)ruthenium(II) (ECPR) and molecular oxygen as co-reactant were used supplemented by a hydrogen purge step after every third ALD cycle. The corresponding ALD growth was observed during the entire process by in-situ real-time spectroscopic ellipsometry (irtSE). Blister-free deposition and satisfactory film stack adhesion with no delamination was verified ex situ by scanning electron microscopy (SEM). The deposited copper inside the TSVs was analyzed by focused ion beam (FIB) imaging and X-ray tomography. The Cu ECD filling capability in HAR-TSVs was shown on a film stack of thALD TaxNy thALD Ru seed using a commercial industry standard 300 mm plating tool. A novel blister-free ultra-thin Ru ALD film having good adhesion properties and unique advantages, e. g. high conformity in high-aspect-ratio through-silicon vias large-scale film uniformity over 300 mm wafers, as well as good reproducibility was developed.

High operation temperatures are a main impact factor for long-term reliability. An efficient cooling approach is crucial especially for high performance computing processors (HPC). As reference, the “International Technology Roadmap for Semiconductors” (ITRS) predicted a power consumption of about 700W for data center server processors [1]. Different cooling approaches were investigated already [2]. Unfortunately, current solutions are not sufficient to fulfill high thermal HPC specifications. On one hand, the insufficient cooling performance is raising the chip junction temperature over the critical point. On other hand, the high performance requirements (e.g. low latency time, higher bandwidth) force to use 3D-Integration of components, which is additional raising the heat build-up [3, 4, 5]. Therefore, only the direct integration of a cooling approach within the 3D-stack can eliminate the overheating bottleneck at all. The fluidic cooling approach has a high potential to fulfill the requirements for this direct fluidic integration approach [6]. This work shows the integration and realization of microfluidic features (microfluidic channels and fluidic inlets/outlets) into an interposer. Furthermore we present the integration of this fluidic interposer into a System in Package (SiP) in order to realize a dual side chip cooling for a heat dissipation of 672W (168W/cm-2 which correlates with predicted power consumption of data center server processor according ITRS-Roadmap [1].

Cu-In fine pitch interconnects are a promising approach for low-temperature technologies in 3D heterogeneous integration. With decreasing structure sizes, the solder material is consumed within little joining durations. The resulting interconnection zone completely exists of intermetallic compounds (IMCs). Due to the unqiue properties of Cu-In-IMCs the interconnection quality of Cu-In fine-pitch interconnects can be affected in a quite tremendous manner when processing conditions are altered. In this work, we address the influence of the bonding duration, the bonding pressure as well as the storage time of as-plated Cu-In microbumps prior to the bonding process.

Nanoporous intermetallic compounds (IMCs) are a promising option for interconnects in 3D integration of various electronic components. These combine the high thermal and mechanical stability of Cu-Sn-SLID (solid-liquid interdiffusion) interconnects with a strongly reduced processing time. In this paper we address the influence of the flux on the nanostructure of the interconnects. The further dissolution of Sn from the already known lamellar network of Cu$_{\mathbf{3}}$Sn is reported for the first time and analyzed in detail.

Purpose Cu/Cu diffusion bonding is characterised by high electrical and thermal conductivity, as well as the mechanical strength of the interconnects. But despite a number of advantages, Cu oxidises readily upon exposure to air. To break through the adsorbed oxide-layer high temperature and pressure, long bonding time and inert gas atmosphere are required during the bonding process. This paper aims to present the implementation of an organic self-assembled monolayer (SAM) as a temporary protective coating that inhibits Cu oxidation. Design/methodology/approach Information concerning elemental composition of the Cu surface has been yielded by X-ray photoelectron spectroscopy (XPS) and Fourier-transform infrared (FTIR) spectroscopy. Two types of substrates (electroplated and sputtered Cu) are prepared for thermocompression bonding in two different ways. In the first case, Cu is cleaned with dilute sulphuric acid to remove native copper oxide. In the second case, passivation with SAM followed the cleaning step with dilute sulphuric acid. Shear strength, fracture surface, microstructure of the received Cu/Cu interconnects are investigated after the bonding procedure. Findings The XPS method revealed that SAM can retard Cu from oxidation on air for at least 12 h. SAM passivation on the substrates with sputtered Cu appears to have better quality than on the electroplated ones. This derives from the results of the shear strength tests and scanning electron microscopy (SEM) imaging of Cu/Cu interconnects cross sections. SAM passivation improved the bonding quality of the interconnects with sputtered Cu in comparison to the cleaned samples without passivation. Originality/value The Cu/Cu bonding procedure was optimised by a novel preparation method using SAMs which enables storage and bonding of Si-dies with Cu microbumps at air conditions while remaining a good-quality interconnect. The passivation revealed to be advantageous for the smooth surfaces. SEM and shear strength tests showed improved bonding quality for the passivated bottom dies with sputtered Cu in comparison to the samples without SAM.

With decreasing solder volumes and joint sizes, new aspects in electronics packaging occur. Previous publications report porous structures in Cu/Sn microbump interconnects after flux-assisted bonding and storage. The origin and mechanisms of pore formation are still discussed among researchers. In this study, the influence of no-clean flux during isothermal storage is investigated on soldered Cu/SnAg3.5 microbumps with intermetallic compounds. Soldering was carried out on single dies in air atmosphere without cleaning agent at 240 °C for 15 min. Subsequent isothermal storage was performed in air and N2 atmosphere at 240 °C for 1 min, 10 min and 20 min. The microbumps were exposed to flux and flux fumes during isothermal storage. Reference samples were stored separately without any flux contact. The results show pores in samples with flux contact of any kind. Inert atmosphere seems to diminish pore formation. The study reveals different residue appearances on and around the microbumps according to different storage conditions. Reasons for pore formation are also discussed in this study.

3D-integration is one of the most challenging approaches addressed by researchers in the field of microelectronics in the recent years. With the intension on integrating different components in three dimensions in one device performance and functionality will increase dramatically by reducing the devices footprint. A major challenge in 3D-integration concepts is the electrical interconnection of the stacked individual components. These interconnecting technologies employ micro bumping, temporary wafer bonding, wafer thinning and through silicon vias (TSVs). The increasing complexity and the miniaturization result in new requirements on testing, diagnostics, failure analysis and metrology techniques, methods and tools. Scanning acoustic microscopy (SAM) is a powerful tool for non-destructively inspecting internal structures and features. It employs elastic waves that can be focused and used for imaging and quantitative analyses. However, at conventionally used frequencies (5 MHz – 250 MHz) imaging resolution compromises the application on devices and technologies required in 3D-integration approaches. The current paper reports on the use of acoustic GHz-microscopy for the inspection, defect localization and its ability for identification of abnormalities in through silicon vias. Investigated were artificial and real defects in the TSV-fillings (voids) and the condition of the TSV-walls (rim-delaminations). Acoustic frequencies used in the current work ranged from 400 MHz up to 1.2 GHz allowing for imaging resolutions in the 1 µm - regime. However, highly focused acoustical lenses as employed here require large numerical apertures which inevitably result in a very complex wave propagation and acoustic field inside a solid sample. To improve the understanding and interpretation acoustic intensity fields have been simulated numerically. Results obtained by acoustic GHz-microscopy have been evaluated complimentarily by FIB-cross-sectioning and SEM imaging which gave a valuable insight into the abilities for acoustic TSV-inspection by GHz-SAM.

In this paper, analytical, numerical-, and measurement-based methods for extracting the resistance, inductance, capacitance, and conductance of through silicon vias (TSVs) are classified, quantified, and compared from 100 MHz to 100 GHz. An in-depth analysis of the assumptions behind these methods is made, from which their limits of accuracy/validity are defined. Based on this, the most reliable methods within the studied frequency range are proposed. The TSVs are designed, fabricated, and measured. Very good correlation is obtained between electrical parameters of the TSVs extracted from the measurements and electromagnetic field simulations.

In this paper we present the process and electrical results of a 3D integration using through silicon vias (TSV). A flash memory chip has been directly connected to a processor die. The TSVs have been applied from the wafer front-side into a fully processed advanced CMOS 300 mm wafers using a via last approach. After dry etching the 20 by 107 μm holes into the substrate an isolation and barrier seed films are deposited and then filled with copper. The electrical connection between the pad level of the processor chips and the interface to the external connections is realized with a two level redistribution wiring. Subsequently the wafer is flipped, temporary bonded to a carrier wafer, thinned and the TSVs are connected from the wafer backside. Finally the flash chips are assembled to the controller die using a die-to-wafer (D2W) technique. Electrical tests have been conducted and a high yield after TSV processing and assembly determined. The isolation properties and electrical resistance was measured. The linear current in stress transistors was used to define a keep out zone.

Some mobile applications require non volatile memories and very small spatial dimensions. The investigation results discussed in this paper are related to a via-last TSV integration scheme where a standard flash memory is connected to the backside of a processor chip (PC) using the through silicon via (TSV) technology. Special focus was given to the realization of chip interconnects between processor chip and the memory. This paper presents the process of the TSV formation starting with a photo resist deposition till TSV fill realized by electro-chemical copper deposition (ECD) and briefly the manufacturing of the redistribution layers as well the die-to-wafer (D2W) assembly of the flash chips. Electrical results will be presented showing the quality of the TSV isolation, the effect of the TSVs on its adjacencies and the quality of the interconnects for the case of flash chips attached to the frontside of the processor wafer (PW).

In information and communication technology, the future has already begun. The transfer of vast amounts of data is routinely done via the Internet, and mobile or portable multiple-use devices or workstations ensure that the information we require is at ready hand, anywhere and at any time. System integration technologies and the Internet as a user platform will soon succeed to be even more integral parts of our daily lives, at work as well as in the home. The trend in PC or smaller device development tends towards ever tinier, ever more complex and autonomous systems, which communicate via interfaces. This means that their miniaturization is quickly advancing and eventually leading to integrated 3D-microsystems of very few cubic millimeters only. The project "Self-sufficient distributed microsystems - AVW" aims to investigate certain aspects of and technologies for these systems as well as to develop solutions which will make a significant contribution to meeting the challenges presented by them.

Autarke verteilte Mikrosysteme stellen durch ihre Kompaktheit eine besondere Herausforderung an die Aufbau- und Verbindungstechnik. Durch die Anforderung, eine Systemintegration in einem definierten Volumen vorzunehmen, sind Technologien, die einen 3 dimensionalen Aufbau ermöglichen, nötig. Die Minimierung des Platzbedarfes der passiven Komponenten wie Spulen, Widerstände, Kondensatoren und Filter in solchen Systemen ist ein wesentlicher technologischer Ansatzpunkt zur Volumenreduktion. Eine Möglichkeit, die 3D Integration durchzuführen, ist die Verwendung von dünnen flexiblen Verdrahtungsträgern, die über Bump-Padverbindungen zu einem dreidimensionalen Gesamtsystem gestapelt werden können. Diese Verdrahtungsträger werden in einem Dünnfilmprozess auf Trägerwafern als Kupfer / Polyimid Mehrlagenverdrahtungsystem hergestellt. Die passiven Komponenten werden dabei integriert. Die Einheiten werden durch Sägen getrennt und durch Ablösen einer Opferschicht, die als erste Lage des Dünnfilmaufbaus gewählt wurde, vom Trägermaterial vereinzelt. Der Entwurf des Demonstrators mit den passiven Komponenten sowie dessen technologische Realisierung werden ausführlich beschrieben. Abschließend werden erste Ergebnisse der Integration der passiven Komponenten in den flexiblen Schaltungsträger präsentiert.