1. The Next Generation Of Exascale-Class Systems: The Exanest Project
- Author
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R. Ammendolay, A. Biagioni, P. Cretaro, O. Frezza, F. Lo Cicero, A. Lonardo, M. Martinelli, P. S. Paolucci, E. Pastorelli, F. Simula, P. Vicini, G. Taffoni, J. Goodacree, M. Lujn, J. Navaridas, J. P. Saiz, N. Chrysos, and M. Katevenis
- Subjects
rack prototype ,non-volatile memory ,Exascale system ,Horizon 2020 ,Euratom ,real HPC applications ,supercomputer ,European Union ,7. Clean energy ,low-latency interconnect ,Euratom research & training programme 2014-2018 - Abstract
The ExaNeSt project started on December 2015 and is funded by EU H2020 research framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux-based power-efficient 64-bit ARM processors clusters for Exascale-class systems. The ExaNeSt consortium pools partners with industrial and academic research expertise in storage, interconnects and applications that share a vision of an European Exascale-class supercomputer. Their goal is designing and implementing a physical rack prototype together with its cooling system, the storage non-volatile memory (NVM) architecture and a low-latency interconnect able to test different options for interconnection and storage. Furthermore, the consortium is to provide real HPC applications to validate the system. Herein we provide a status report of the project initial developments., To appear in: the Proceedings of the Euromicro Conference on Digital System Design (DSD 2017), Vienna, Austria, 30 August - 1 September, 2017