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The allocation of resources and scheduling of tasks, specifically mapping, in multicore systems on-chip (MCSoC), poses significant challenges. Tasks have diverse resource requirements and interact with each other, while network-on-chip (NoC)-based MCSoC consists of heterogeneous cores and communication networks. The heterogeneity of resources in MCSoC, along with the varying computational and communication demands of applications, makes mapping a complex optimization problem. We have mathematically modeled the mapping problem in NoC-based MCSoC using mixed-integer linear programming (MILP) with the objective of minimizing the execution time of applications. This model incorporates computation and communication capacity, energy budget constraints of MCSoC, and execution time requirements of applications. We further propose heuristics, including simulated annealing (SA) and genetic algorithm (GA), considering the capacity and budget constraints of MCSoC systems to accelerate applications and provide quick mapping solutions. Simulation results demonstrate that the performance from SA and GA heuristics is very close (within 10%) to the optimal solutions from MILP across various applications for 2D-Mesh NoCs with 16–100 cores. The energy consumption of SA and GA heuristics is also very close to the optimal solutions from MILP, with a few exceptions on small-scale 16-core NoC. Additionally, SA outperforms GA in most cases for all applications. [ABSTRACT FROM AUTHOR]

As a result of frequency and power limitations, multi-core processors and accelerators are becoming more and more prevalent in today's systems. To fully utilize such systems, heterogeneous parallel programming is needed, but this introduces new complexities to the development. High-level frameworks such as SkePU have been introduced to help alleviate these complexities. SkePU is a skeleton programming framework based on a set of programming constructs implementing computational parallel patterns, while presenting a sequential interface to the programmer. Using the various skeleton backends, SkePU programs can execute, without source code modification, on multiple types of hardware such as CPUs, GPUs, and clusters. This paper presents the design and implementation of a new backend for SkePU, adding support for FPGAs. We also evaluate the effect of FPGA-specific optimizations in the new backend and compare it with the existing GPU backend, where the actual devices used are of similar vintage and price point. For simple examples, we find that the FPGA-backend's performance is similar to that of the existing backend for GPUs, while it falls behind in more complex tasks. Finally, some shortcomings in the backend are highlighted and discussed, along with potential solutions. [ABSTRACT FROM AUTHOR]

This work tackles the performance and energy consumption analysis of a legacy scientific application, the VASP (Vienna Ab-initio Simulation Package), an application commonly used by physicists and chemists for modeling materials at the atomic scale. Many of these scientific applications have been implemented in Fortran, where energy metrics instrumentation is not straightforward. We obtained performance figures (execution time and energy consumption) by instrumenting the source code using EML. This energy measurement library has been modified to introduce Fortran interfaces for these metrics. The analysis was carried out using different matrix algebra libraries, parallelization techniques, and hardware platforms, emphasizing on the MPI, OpenMP, and CUDA parallel implementations of the algorithms used in VASP. We employ various material specifications (atomic structures) and molecular sizes of a silicon-based crystal to create a set of benchmarks for these specifications, leading to some recommendations for final users regarding performance improvements. The proposed benchmarking technique assists the user in selecting the right combination of problem size, compilers, and parallelization options available in VASP. For a given system platform, the user will be able to determine not only the architecture to use (GPU or multicore processors), but also the appropriate library and parallelization according to the atomic structure and molecular size. [ABSTRACT FROM AUTHOR]

The discovery of Allele-Specific Methylation (ASM) is an important research field in biology as it regulates genomic imprinting, which has been identified as the cause of some genetic diseases. Nevertheless, the high computational cost of the bioinformatic tools developed for this purpose prevents their application to large-scale datasets. Hence, much faster tools are required to further progress in this research field. In this work we present PARamrfinder, a parallel tool that applies a statistical model to identify ASM in data from high-throughput short-read bisulfite sequencing. It is based on the state-of-the-art sequential tool amrfinder, which is able to detect ASM at regional level from Bisulfite Sequencing (BS-Seq) experiments in the absence of Single Nucleotide Polymorphism information. PARamrfinder provides the same Allelically Methylated Regions as amrfinder but at significantly reduced runtime thanks to exploiting the compute capabilities of common multicore CPU clusters and MPI RMA operations to attain an efficient dynamic workload balance. As an example, our tool is up to 567 times faster for real data experiments on a cluster with 8 nodes, each one containing two 16-core processors. The source code of PARamrfinder, as well as a reference manual, is available at https://github.com/UDC-GAC/PARamrfinder. [ABSTRACT FROM AUTHOR]

The automotive industry has recently adopted multicore processors and microcontrollers to meet the requirements of new features, such as autonomous driving, and comply with the latest safety standards. However, inter-core communication poses a challenge in ensuring real-time requirements such as time determinism and low latencies. Concurrent access to shared buffers makes predicting the flow of data difficult, leading to decreased algorithm performance. This study explores the integration of Logical Execution Time (LET) and Time-Division Multiple Access (TDMA) models in multicore embedded systems to address the challenges in inter-core communication by synchronizing read/write operations across different cores, significantly reducing latency variability and improving system predictability and consistency. Experimental results demonstrate that this integrated approach eliminates data loss and maintains fixed operation rates, achieving a consistent latency of 11 ms. The LET-TDMA method reduces latency variability to approximately 1 ms, maintaining a maximum delay of 1.002 ms and a minimum delay of 1.001 ms, compared to the variability in the LET-only method, which ranged from 3.2846 ms to 8.9257 ms for different configurations. [ABSTRACT FROM AUTHOR]

The recent shift in the VLSI industry from conventional MOSFET to FinFET for designing contemporary chip-multiprocessor (CMP) has noticeably improved hardware platforms' computing capabilities, but at the cost of several thermal issues. Unlike the conventional MOSFET, FinFET devices experience a significant increase in circuit speed at a higher temperature, called temperature effect inversion (TEI), but higher temperature can also curtail the circuit lifetime due to self-heating effects (SHEs). These fundamental thermal properties of FinFET introduced a new challenge for scheduling time-critical tasks on FinFET-based multicores that how to exploit TEI towards improving performance while combating SHEs. In this work, TREAFET, a temperature-aware real-time scheduler, attempts to exploit the TEI feature of FinFET-based multicores in a time-critical computing paradigm. At first, the overall progress of individual tasks is monitored, tasks are allocated to the cores, and finally, a schedule is prepared. By considering the thermal profiles of the individual tasks and the current thermal status of the cores, hot tasks are assigned to the cold cores and vice-versa. Finally, the performance and temperature are balanced on-the-fly by incorporating a prudential voltage scaling towards exploiting TEI while guaranteeing the deadline and thermal safety. Moreover, TREAFET stimulates the average runtime frequency by employing an opportunistic energy-adaptive voltage spiking mechanism, in which energy saving during memory stalls at the cores is traded off during the time slice having the spiked voltage. Simulation results claim TREAFET maintains a safe and stable thermal status (peak temperature below 80 °C) and improves frequency up to 17% over the assigned value, which ensures legitimate time-critical performance for a variety of workloads while surpassing a state-of-the-art technique. The stimulated frequency in TREAFET also finishes the tasks early, thus providing opportunities to save energy by power gating the cores, and achieves a 24% energy delay product (EDP) gain on average. [ABSTRACT FROM AUTHOR]

We address the efficient implementation of the convolution operator on the GAP8 parallel ultra-low power platform (PULP), a heterogeneous multi-core processor equipped with a fabric controller (FC); a cluster of eight compute cores; and a four-level memory hierarchy with scratchpads instead of conventional, hardware-assisted cache memories. Our solution for this platform transforms the convolution into a general matrix–matrix multiplication (gemm) via the lowering approach, demonstrating that it is possible to attain reasonable performance on the GAP8 by carefully adapting techniques such as tiling and loop parallelism, which are mainstream in the multi-threaded, cache-aware realization of gemm. [ABSTRACT FROM AUTHOR]

Mobile devices and handheld systems, such as the smartphones and tablets universally extended, are becoming increasingly powerful. Their basic hardware configuration is usually state-of-the-art heterogeneous architectures consisting of multi-core processors and some kind of accelerator such as GPUs or DSPs. Specific code adapted to the architecture is mandatory if high-performance computation is required and low-level libraries and parallelism are needed, which constitutes an important barrier for the usual developer in such devices. In this context, we propose the FancyJCL framework. It provides a high-level abstraction layer that hides implementation details and allows to develop parallel programs for mobile devices. The target platform for FancyJCL is mainly Android and Java developers due to their high market penetration. A very simple, seemingly sequential encoding results in parallel efficient OpenCL code. FancyJCL is itself based on the Fancier framework, which enables optimal memory management across memory spaces on unified memory systems. Benchmarks of FancyJCL code developed for a wide range of image processing algorithms show good performance with low development effort. [ABSTRACT FROM AUTHOR]

Currently, the digitization of environment objects (vegetation, terrain, architectural structures, etc.) in the form of point clouds is actively being developed. The integration of such digitized objects into virtual environment systems allows the quality of the modeled environment to be improved, but requires efficient methods and algorithms for real-time visualization of large point volumes. In this paper the solution of this task on modern multicore GPUs with support of hardware-accelerated ray tracing is researched. A modified method is proposed where the original unordered point cloud is split up into point groups whose visualization is effectively parallelized on ray tracing cores. The paper describes an algorithm for constructing such groups using swapping arrays of point indices, which works faster than alternative solutions based on linked lists, and also has lower memory overhead. The proposed method and algorithm were implemented in point cloud visualization software complex and approbated on a number of digitized environment objects. The results of the approbation confirmed the efficiency of proposed solutions as well as their applicability for virtual environment systems, video simulators, geoinformation systems, virtual laboratories, etc. [ABSTRACT FROM AUTHOR]

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Lightweight cryptographic algorithms like Speck, which are a family of block ciphers developed by the US National Security Agency (NSA), have become popular because of their efficient performance and small operational size. This paper introduces the execution on a parallel multi-core processor of the optimized version of the Speck cipher. However, this proposition fulfils the increased demand for developing quick and ultra-lightweight ciphers. In this work, this is addressed by optimizing the speck128/128 cipher by reducing its number of rounds to five. The optimization is accomplished by adding the dynamic substitution layer to increase the randomness of the cipher, which allows us to reduce the speck rounds. We conducted tests such as statistical, randomness, and cryptanalysis tests for linear and differential attacks on the optimized speck. The security results show that the optimized speck overcomes the original speck security level. The conducted experiments show that the new version of the speck runs faster than the original one in terms of execution time and throughput. The parallel execution over a multicore processor is applied, and its speedup ratio is equal to 2.64 when it's compared to the parallel execution of the original speck. Different message sizes and thread configurations are used in this work. The sequential execution of both speck ciphers is computed in terms of execution time and throughput, and the acceleration ratio of the optimized speck in this case is equal to 2.63. [ABSTRACT FROM AUTHOR]

Popular blockchains such as Ethereum and several others execute complex transactions in the block through user-defined scripts known as smart contracts. Serial execution of smart contract transactions/atomic units (AUs) fails to harness the multiprocessing power offered by the prevalence of multi-core processors. By adding concurrency to the execution of AUs, we can achieve better efficiency and higher throughput. In this paper, we develop a concurrent miner that proposes a block by executing AUs concurrently using optimistic Software Transactional Memory systems (STMs). It efficiently captures independent AUs in the concurrent bin and dependent AUs in the block graph (BG). Later, we propose a concurrent validator that re-executes the same AUs concurrently and deterministically using the concurrent bin followed by the BG given by the miner to verify the block. We rigorously prove the correctness of concurrent execution of AUs. The performance benchmark shows that the average speedup for the optimized concurrent miner is 5.21 × , while the maximum is 14.96 × over the serial miner. The optimized validator obtains an average speedup of 8.61 × to a maximum of 14.65 × over the serial validator. The proposed miner outperforms 1.02 × to 1.18 × , while the proposed validator outperforms 1 × to 4.46 × over state-of-the-art concurrent miners and validators, respectively. Moreover, the proposed efficient BG saves an average of 2.29 × more block space when compared with the state-of-the-art. [ABSTRACT FROM AUTHOR]

To the complexity of networks and the diversity of circuits, multicore embedded sensing systems suffer from low accuracy and efficiency in measuring temperature. To improve the measurement accuracy and efficiency of multicore embedded sensing systems, this paper utilised knowledge distillation, model pruning and parameter quantisation to lightweight neural networks. Meanwhile, the lightweight neural network was applied to multicore embedded sensing systems and the layout of multicore embedded sensing systems based on it was analysed from the perspectives of processor layout, storage design and link network, providing a reference and theoretical basis for further application of multicore embedded sensing systems. [ABSTRACT FROM AUTHOR]

CAMP proposes a hierarchical cache subsystem for multi-core mixed criticality processors, focusing on ensuring worst-case execution time (WCET) predictability in automotive applications. It incorporates criticality-aware locked L1 and L2 caches, reconfigurable at mode change intervals, along with criticality-aware last level cache partitioning. Evaluation using CACOSIM, Moola Multicore simulator, and CACTI simulation tools confirms the suitability of CAMP for keeping high-criticality jobs within timing budgets. A practical case study involving an automotive wake-up controller using the sniper v7.2 architecture simulator further validates its usability in real-world mixed criticality applications. CAMP presents a promising cache architecture for optimized multi-core mixed criticality systems. [ABSTRACT FROM AUTHOR]

Summary: We consider automatic performance tuning of dense symmetric eigenvalue problems using ATMathCoreLib, which is a library to assist automatic tuning. We deal with two problems, namely, automatic code selection for the symmetric generalized eigenvalue problem in distributed‐memory parallel environments and automatic parameter tuning in tridiagonalization of dense symmetric matrices on multicore processors. As for the first problem, numerical experiments show that ATMathCoreLib can choose the fastest solver for a given computing environment and problem size quickly even if the fluctuation in the execution time is as high as 40%. As for the second problem, ATMathCoreLib was able to select nearly optimal combinations of the algorithm and its parameter reliably and efficiently for various computing environments and matrix sizes. The performance of auto‐tuning was further enhanced by incorporating a user‐provided execution‐time model into ATMathCoreLib. [ABSTRACT FROM AUTHOR]

Electric vehicles (EVs) are becoming more and more popular as they provide significant environmental benefits compared to fossil-fuel vehicles. However, they represent substantial loads on the power grid, and the scheduling of EV charging can be a challenge, especially in large parking lots. This paper presents a metaheuristic-based approach parallelized on multicore processors (CPU) and graphics processing units (GPU) to optimize the scheduling of EV charging in a single smart parking lot. The proposed method uses a particle swarm optimization algorithm that takes as input the arrival time, the departure time, and the power demand of the vehicles and produces an optimized charging schedule for all vehicles in the parking lot, which minimizes the overall charging cost while respecting the chargers' capacity and the parking lot feeder capacity. The algorithm exploits task-level parallelism for the multicore CPU implementation and data-level parallelism for the GPU implementation. The proposed algorithm is tested in simulation on parking lots containing 20 to 500 EVs. The parallel implementation on CPUs provides a speedup of 7.1x, while the implementation on a GPU provides a speedup of up to 247.6x. The parallel implementation on a GPU is able to optimize the charging schedule for a 20-EV parking lot in 0.87 s and a 500-EV lot in just under 30 s. These runtimes allow for real-time computation when a vehicle arrives at the parking lot or when the electricity cost profile changes. [ABSTRACT FROM AUTHOR]

Benchmarks play an essential role in the performance evaluation of novel research concepts. Their effectiveness diminishes if they fail to exploit the available hardware of the evaluated microprocessor or, more broadly, if they are not consistent in comparing various systems. An empirical analysis of the consecrated Splash-2 benchmarks suite vs. the latest version Splash-4 was performed. It was shown that on a 64-core configuration, half of the simulated benchmarks reach temperatures well beyond the critical threshold of 105 °C, emphasizing the necessity of a multi-objective evaluation from at least the following perspectives: energy consumption, performance, chip temperature, and integration area. During the analysis, it was observed that the cores spend a large amount of time in the idle state, around 45% on average in some configurations. This can be exploited by implementing a predictive dynamic voltage and frequency scaling (DVFS) technique called the Simple Core State Predictor (SCSP) to enhance the Intel Nehalem architecture and to simulate it using Sniper. The aim was to decrease the overall energy consumption by reducing power consumption at core level while maintaining the same performance. More than that, the SCSP technique, which operates with core-level abstract information, was applied in parallel with a Value Predictor (VP) or a Dynamic Instruction Reuse (DIR) technique, which rely on instruction-level information. Using the SCSP alone, a 9.95% reduction in power consumption and an energy reduction of 10.54% were achieved, maintaining the performance. By combining the SCSP with the VP technique, a performance increase of 8.87% was obtained while reducing power and energy consumption by 3.13% and 8.48%, respectively. [ABSTRACT FROM AUTHOR]

Summary: As the development of chip manufacturing technology slows down, high‐performance processors often have high energy consumption and high heat generation. Therefore, heterogeneous multi‐core processors become more and more popular, and the heterogeneous multi‐core processors is adopted to execute programs. At present, the general program consists of multiple threads. To reach goals of accelerating program execution and reducing energy consumption and heat generation of system, a suitable thread scheduling algorithm for heterogeneous multi‐core processors is needed. In this article, a thread scheduling algorithm based on multiple critical scheduling factors is proposed. First, a prediction model of thread performance and energy consumption is used to predict the core sensitivity of threads. Then, critical threads are judged and accelerated by collecting the synchronization information between threads. Finally, the load balancing method based on the computing power of cores and the core sensitivity of threads is employed to perform system load balancing, which ensures the fairness of the scheduling. Several experiments are provided, and the results show that the proposed algorithm can obtain better performance of thread schedule. [ABSTRACT FROM AUTHOR]

Four‐Wave Mixing (FWM) is one of the non‐linear phenomena affecting long‐reach communication systems and high bandwidth. Research communities use simulation tools for parameter optimization. Unfortunately, such a simulation is time‐consuming and requires more time as the number of channels increases. This paper proposes two fast implementations of Dense Wavelength Division Multiplexing (DWDM) system, limited by FWM and the intrinsic Amplified Spontaneous Emission (ASE) noise of optical amplifiers employed in each segment. Additionally, this work compares the efficiency and speed improvement of the proposed parallelization model versus an earlier sequential model. We present the computational complexity analysis of sequential and parallel models. The paper considers two different parallel implementations: a multicore processor using Open MultiProcessing (OpenMP) and Compute Unified Device Architecture (CUDA), which is based on the use of a Graphics Processing Unit (GPU). Results show that parallelism using CUDA improves by up to 70 times the simulation performance compared to the sequential model. Parallelism with CUDA is up to 15 times compared to OpenMP using 12 logical processors. It is possible to simulate an increased number of channels within our parallel execution, which was impractical in the sequential simulation. [ABSTRACT FROM AUTHOR]

Modern electronic devices are supported by multicore processors and they have become an unavoidable part of recent technologies. The Arithmetic Logic Unit (ALU) is one of the indispensable parts of the Central Processing Unit (CPU) which performs most of the operations. Operations like multiplications, and exponentials consume more power than other normal operations. Power management is one of the major challenges in designing processors. To maximize speed and reduce power consumption, a new technique in Multiplier and ALU incorporated with a multicore processor has been proposed. The Proposed Approximate Compatible ALU (ACALU) is designed to perform specified operations that consume more power, using an advanced multiplication technique called the First One First Operand (FOFO) method. The selection process of eight bits is done by the FOFO method followed by error detection and error approximation is performed to get the accurate output. The ACALU performs these operations in the Approximate Computing Mode which utilizes only eight bits for the operations, thus reducing the power consumption. The results of several analyses between multipliers, ALUs, and microprocessors are provided. As we optimize the multiplier and ALU unit, the multicore processor is also enhanced. The proposed multicore processor is compared with the AMD processor and the latest INTEL processor and the comparison results show that the proposed technique is 95.2% and 97.8% more efficient than the existing processors. Thus, the power consumption is minimized and the performance speed is increased in the proposed multicore processor. [ABSTRACT FROM AUTHOR]

The authors formalize the technique of interactive evaluation of the operation efficiency of the motor vehicle system of a large city based on U-statistics methods. To optimize this technique, the authors propose efficient algorithmic constructions for parallel execution of local, aggregated, and prognostic evaluation of the system's components using modern computers, namely, multi-core computers, clusters, hybrid architectures, and high-performance computing environments. The obtained scientific results allow for real-time evaluation of the operation efficiency of the city motor vehicle system. [ABSTRACT FROM AUTHOR]

Malleability is defined as the ability to vary the degree of parallelism at runtime, and is regarded as a means to improve core occupation on state-of-the-art multicore processors tshat contain tens of computational cores per socket. This property is especially interesting for applications consisting of irregular workloads and/or divergent executions paths. The integration of malleability in high-performance instances of the Basic Linear Algebra Subprograms (BLAS) is currently nonexistent, and, in consequence, applications relying on these computational kernels cannot benefit from this capability. In response to this scenario, in this paper we demonstrate that significant performance benefits can be gathered via the exploitation of malleability in a framework designed to implement portable and high-performance BLAS-like operations. For this purpose, we integrate malleability within the BLIS library, and provide an experimental evaluation of the result on three different practical use cases. [ABSTRACT FROM AUTHOR]

The problem of the interferometric phase unwrapping in radar remote sensing of Earth systems is considered. Such interferograms are widely used in the problems of creating and updating maps of the relief of the Earth's surface in geodesy, cartography, environmental monitoring, geological, hydrological and glaciological studies, and for monitoring transport communications. Modern radar systems have ultra-high spatial resolution and a wide band, which leads to the need to unwrap large interferograms from several tens of millions of elements. The implementation of calculations by these methods requires a processing time of several days. In this paper, an effective method for equalizing the inverse vortex field for phase unwrapping is proposed, which allows solving a problem with quasi-linear computational complexity depending on the interferogram size and the number of singular points on it. To implement the method, a parallel algorithm for solving the problem on a multi-core processor using OpenMP technology was developed. Numerical experiments on radar data models were carried out to investigate the effectiveness of the algorithm depending on the size of the source data, the density of singular points and the number of processor cores. [ABSTRACT FROM AUTHOR]

Due to Covid pandemic, the investigation of bioinformatics, and more specifically the investigation of RNA, has become a major focus of the research. mRNA-based vaccines have been developed by a significant number of academician and scientists. When a virus infects a human body, it first causes disruption to the host's RNA structure, then it transforms the host's RNA into its own genetic structure. As a result, it is vital to research on the process of making predictions about the secondary structures of RNA. The process of predicting the secondary structure of long RNA sequences takes a significant amount of time. This study makes a contribution to the implementation of the algorithm that finds the predicted secondary structure. The methodology for RNA secondary prediction that was employed in this study is based on a dynamic programming model that uses shared memory multicore architecture. The Nearest Neighbor Thermodynamic Model (NNTM) is used as the foundation for the determination of the least amount of free energy. The Gutell database has been used for the RNA sequences of a number of different bacterial species. A comparison was made between the amount of time required to identify the secondary structure of RNA. The length of the RNA sequence is a factor that affects the performance of many existing methods, but the proposed GAfold technique handles sequences of any length. Once the secondary structure has been identified, it helped to detect the virus. It is discovered that the GAfold approach speeds up RNA Secondary structure's prediction. The proposed GAfold algorithm offers a speed increase factor of 2.5 ns on a four-core architecture, 3.09 ns on an eight-core design, and 5.5 ns on a twelve-core architecture. It has been shown that predicting suboptimal structures enhanced the accuracy of the free energy minimization algorithm, which in turn improved the accuracy of full RNA. [ABSTRACT FROM AUTHOR]

Phylogenies are central to many research areas in biology and commonly estimated using likelihood-based methods. Unfortunately, any likelihood-based method, including Bayesian inference, can be restrictively slow for large datasets—with many taxa and/or many sites in the sequence alignment—or complex substitutions models. The primary limiting factor when using large datasets and/or complex models in probabilistic phylogenetic analyses is the likelihood calculation, which dominates the total computation time. To address this bottleneck, we incorporated the high-performance phylogenetic library BEAGLE into RevBayes , which enables multi-threading on multi-core CPUs and GPUs, as well as hardware specific vectorized instructions for faster likelihood calculations. Our new implementation of RevBayes+BEAGLE retains the flexibility and dynamic nature that users expect from vanilla RevBayes. In addition, we implemented native parallelization within RevBayes without an external library using the message passing interface (MPI); RevBayes+MPI. We evaluated our new implementation of RevBayes+BEAGLE using multi-threading on CPUs and 2 different powerful GPUs (NVidia Titan V and NVIDIA A100) against our native implementation of RevBayes+MPI. We found good improvements in speedup when multiple cores were used, with up to 20-fold speedup when using multiple CPU cores and over 90-fold speedup when using multiple GPU cores. The improvement depended on the data type used, DNA or amino acids, and the size of the alignment, but less on the size of the tree. We additionally investigated the cost of rescaling partial likelihoods to avoid numerical underflow and showed that unnecessarily frequent and inefficient rescaling can increase runtimes up to 4-fold. Finally, we presented and compared a new approach to store partial likelihoods on branches instead of nodes that can speed up computations up to 1.7 times but comes at twice the memory requirements. [ABSTRACT FROM AUTHOR]

In the present era, energy is progressively turning into the major limitation in designing multicore chips. However, power and performance are the primary segments of energy, which are contrarily correlated in multicore architectures. This research primarily focused on optimizing energy level of multicore chips using parallel workloads by utilizing either power or execution advancement based on machine learning computation on dynamic programming. To do as such, the novel dynamic machine learning‐based heuristic energy optimization (DML‐HEO) algorithm has been designed and developed in this research on application‐specific controllers to optimize energy‐level on multicore architecture. Here DML‐HEO is implemented on the controller to maximize the execution inside a fixed power spending plan or to limit the expended capacity to accomplish a similar pattern execution. The controller is additionally scalable as it does not bring about critical overhead due to the increase in quantity of cores. The strategy has been assessed utilizing controllers on a full‐framework test system at lab‐scale analysis. The experimental results demonstrate that our proposed DML‐HEO system shows improving performance than the traditional system. [ABSTRACT FROM AUTHOR]

Wireless Network-on-Chip (WNoC) incorporating on-chipantennas has emerged as a promising alternative to overcome the communication bottleneck due to high frequency operation, propagation delay, crosstalk delay, noise and need for repeaters inwired interconnects in chip-multiprocessors (CMPs). Recent advancements in nano materials, such as graphene have enabled the development of novel plasmonic graphene devices, which intrinsically operate in THz band. This ultra-low power andcompact graphene-based nano-antennas (GNA) establishes ultra-high bandwidth THz-on-chip wireless links for intra/inter-chip communication. In this article, we design and simulate a novel fork-shaped planarplasmonic nano-patch antenna using grapheneon SiO2/Si substrate that can be integrated into transceivers working at THz frequencies operating from 0.5 THz to 2.6 THz. By simulation at THz band, proposed antenna performance as a wireless inter/intra-chip link is investigated by numericallyobtaining itssignal transmission coefficient characteristics between the two on-chip antennas, acting as transmitter and receiver or vice-verse for short-range THz communication among wireless NoC based multi-core processors integrated on same substrate. Theresults are obtained by placing the antennas in broadside orientation, that can communicate with intra-chip transmission coefficients ranging from − 20 dB to − 60 dB while sustaining bandwidths upto 0.13–0.2 THz. Further, the effect of transmission and radiation performance of proposed antennas with increase in distance dlink is studied along with reconfigurable nature of graphene with varying chemical potentials from 0.1 eV − 0.5 eV. Proposed antenna has obtained maximum gain and radiation efficiency of 3.89 dB and 58% at 1.83 THz when chemical potential of 0.1 eV is applied. This concept can broadly be applied to future systems as it can be directly integrated into transceivers as graphene is compatible with CMOS processes.Fabrication process steps of proposed on-chip antenna and its feasibility as a real device in chip environment isalso discussed. [ABSTRACT FROM AUTHOR]

Graphs are the most complex data structure that involves heavy mathematical computations. Various real-time applications use the graph at storage, processing, object characterization, and behavior specification stages. The connectivity analysis, coverage building, and routing are the critical applications of graph evaluation. Various associated applications need the exploration of a graph with a practical and real-time outcome. The processing of larger graphs is a big challenge for the researcher. In this paper, a hybrid graph-based computation optimization method is designed to optimize the performance of graph processing in multi-core processors. The BFS algorithm is applied over the multiple processors to optimize the functional response. The multithreaded-BFS is implemented to reduce the time of graph processing and computation. The proposed algorithm is implemented in the OpenMP environment. The experimentation is done on two-core and four-core processors. The experiment is conducted on a 100 to 1000-node network. The traversing and graph coloring algorithms are implemented for the analysis. The comparative analysis is conducted on single-core and multi-core processors with DFS and BFS-based algorithms. The analysis results identified that the proposed algorithm reduced the processing time effectively. [ABSTRACT FROM AUTHOR]

Following a conventional design principle that pays more fast-CPU-cycles for fewer slow-I/Os, popular software storage architecture Linux Multiple-Disk (MD) for parity-based RAID (e.g., RAID5 and RAID6) assigns one or more centralized worker threads to efficiently process all user requests based on multi-stage asynchronous control and global data structures, successfully exploiting characteristics of slow devices, e.g., Hard Disk Drives (HDDs). However, we observe that, with high-performance NVMe-based Solid State Drives (SSDs), even the recently added multi-worker processing mode in MD achieves only limited performance gain because of the severe lock contentions under intensive write workloads. In this paper, we propose a novel stripe-threaded RAID architecture, StRAID, assigning a dedicated worker thread for each stripe-write (one-for-one model) to sufficiently exploit high parallelism inherent among RAID stripes, multi-core processors, and SSDs. For the notoriously performance-punishing partial-stripe writes that induce extra read and write I/Os, StRAID presents a two-stage stripe write mechanism and a two-dimensional multi-log SSD buffer. All writes first are opportunistically batched in memory, and then are written into the primary RAID for aggregated full-stripe writes or conditionally redirected to the buffer for partial-stripe writes. These buffered data are strategically reclaimed to the primary RAID. We evaluate a StRAID prototype with a variety of benchmarks and real-world traces. StRAID is demonstrated to outperform MD by up to 5.8 times in write throughput. [ABSTRACT FROM AUTHOR]

Epidermal thickness (ET) changes are associated with several skin diseases. To measure ET, segmentation of optical coherence tomography (OCT) images is essential; manual segmentation is very time-consuming and requires training and some understanding of how to interpret OCT images. Fast results are important in order to analyze ET over different regions of skin in rapid succession to complete a clinical examination and enable the physician to discuss results with the patient in real time. The well-known CNN-graph search (CNN-GS) methodology delivers highly accurate results, but at a high computational cost. Our objective was to build a computational core, based on CNN-GS, able to accurately segment OCT skin images in real time. We accomplished this by fine-tuning the hyperparameters, testing a range of speed-up algorithms including pruning and quantization, designing a novel pixel-skipping process, and implementing the final product with efficient use of core and threads on a multicore central processing unit (CPU). We name this product CNN-GS-skin. The method identifies two defined boundaries on OCT skin images in order to measure ET. We applied CNN-GS-skin to OCT skin images, taken from various body sites of 63 healthy individuals. Compared with CNN-GS, our described method reduced computation time by 130 × with minimal reduction in ET determination accuracy (from 96.38 to 94.67%). [ABSTRACT FROM AUTHOR]

The rapid replacement of PSTN with VOIP networks indicates the definitive phase-out of the PBX/PABX with smartphone-based VOIP technology that uses WLAN connectivity for local communication; however, security remains a key issue, regardless of the communication coverage area. Session initiation protocol (SIP) is one of the most widely adopted VOIP connection establishment protocols but requires added security. On the Internet, different security protocols, such as HTTPS (SSL/TLS), IPSec, and S/MIME, are used to protect SIP communication. These protocols require sophisticated infrastructure and some pose a significant overhead that may deteriorate SIP performance. In this article, we propose the following: i) avoid using Internet bandwidth and complex Internet protocols for local communication within an organization, but harness WLAN connectivity, ii) use multi-threaded or multicore computer systems to handle concurrent calls instead of installing hardware-based SIP servers, and iii) run each thread in a separate core. Cryptography is a key tool for securely transmitting confidential data for long- and short-range communication, and the Diffie-Hellman (DH) protocol has consistently been a popular choice for secret key exchanges. Primarily, used for symmetric key sharing, it has been proven effective in generating public/private key pairs, sharing public keys securely over public channels, and subsequently deriving shared secret keys from private/public keys. This key exchange scheme was proposed to safeguard VOIP communication within WLANs, which rely on the SIP for messaging and multimedia communication. For ensuring an efficient implementation of SIP, the system was rigorously analyzed using the M/M/1 and M/M/c queuing models. We analyze the behavior of SIP servers with queuing models with and without end-to-end security and increase users' trust in SIP security by providing a transparent sense of end-to-end security as they create and manage their private and public keys instead of relying on the underlying SIP technology. This research implements instant messaging, voice conversation, and secret key generation over DH while implementing and observing the role of multi-threading in multiqueue systems that serve incoming calls. By increasing the number of threads from one to two, the SIP response time improved from 20.23809 to 0.08070 min at an arrival rate of 4250 calls/day and a service rate of three calls/min. Similarly, by adding one to seven threads, the queue length was reduced by four calls/min. Implementing secure media streaming and reliable AES-based signaling for session confidentiality and integrity introduces a minor 8-ms tradeoff in SIP service performance. However, the advantages of implementing added security outweigh this limitation. [ABSTRACT FROM AUTHOR]

This paper presents a method based on particle swarm optimization (PSO) for optimizing the power settings of unmanned aerial vehicle (UAVs) along a given trajectory in order to minimize fuel consumption and maximize autonomy during surveillance missions. UAVs are widely used in surveillance missions and their autonomy is a key characteristic that contributes to their success. Providing a way to reduce fuel consumption and increase autonomy provides a significant advantage during the mission. The method proposed in this paper included path smoothing techniques in 3D for fixed-wing UAVs based on circular arcs that overfly the waypoints, an essential feature in a surveillance mission. It used the equations of motions and the decomposition of Newton's equation to compute the fuel consumption based on a given power setting. The proposed method used PSO to compute optimized power settings while respecting the absolute physical constraints, such as the load factor, the lift coefficient, the maximum speed and the maximum amount of fuel onboard. Finally, the method was parallelized on a multicore processor to accelerate the computation and provide fast optimization of the power settings in case the trajectory was changed in flight by the operator. Our results showed that the proposed PSO was able to reduce fuel consumption by up to 25% in the trajectories tested and the parallel implementation provided a speedup of 21.67× compared to a sequential implementation on the CPU. [ABSTRACT FROM AUTHOR]

The slope calculation algorithm is one of the most widely used geospatial algorithms employing the 3x3 moving window technique (along with calculation of aspect, curvature and flow direction). This work presents an approach consisting of transforming a slope algorithm from a sequential form into a version that can exploit vector and parallel traits of multicore architectures with vector instructions. This approach allows us to take advantage of the potential of the modern multicore processors. The basic idea for optimizing the 3x3 moving window computation is to split the equation used to calculate the result into parts that operate on data that are known to exist in adjacent memory locations. The research was conducted on two multicore architectures without the change in the code — the older architecture was Sandy Bridge and the newer one was Haswell (with more cores). The efficiency of the developed slope algorithm was verified in practice with the use of DEM files of the same resolution but of different sizes. We showed through the numerical experiments that our approach gives better time performance than the original algorithm (and other tools) — and with no loss of accuracy. [ABSTRACT FROM AUTHOR]

In system-on-a-chip based complex processors has the problem of multithreading and miss-functionality due to their complexity and high-speed operations. In order to minimize these problems, the proposed design has machine learningbased algorithms and cryptography systems for security has been incorporated. In the proposed work, the security level has been taken care of in three different stages such as data integrity, data authentication, and private and public keys encryption and decryption. In order to increase throughput with minimal latency, the proposed architecture with advanced high-performance protocol and advanced high-performance and advanced peripheral bus bridge is incorporated between the fabric dynamically re configurable multi-processor and peripherals along with security algorithms using secure hash algorithm (SHA-256) bits and advanced encryption standard (AES). In order to perform machine learningbased applications, the proposed system is incorporated double-precision floating point arithmetic operations. The overall proposed architecture is developed in verilog hybrid deep learning (HDL) and quality checking using the LINT tool. The entire design is interfaced with the Zynq processor and software development kit (SDK) tool to verify data transfer between hardware and software. The obtained results are compared with existing state-of-art results and found that 18% improvement in throughput, a 21% improvement in power consumption savings, and a 34% reduction in latency. [ABSTRACT FROM AUTHOR]

Optimal control musculoskeletal simulation is a valuable approach for studying fundamental and clinical aspects of human movement. However, the high computational demand has long presented a substantial challenge, creating a need to improve simulation performance. The OpenSim Moco software package permits musculoskeletal simulation problems to be solved in parallel on multicore processors using the CasADi optimal control library, potentially reducing the computational demand. However, the computational performance of this framework has not been thoroughly examined. Thus, we aimed to investigate the computational speed‐up obtained via multicore parallel computing relative to solving problems serially (i.e., using a single core) in optimal control simulations of human movement in OpenSim Moco. Simulations were solved using up to 18 cores with a variety of temporal mesh interval densities and using two different initial guess strategies. We examined a range of musculoskeletal models and movements that included two‐ and three‐dimensional models, tracking and predictive simulations, and walking and reaching tasks. The maximum overall parallel speed‐up was problem specific and ranged from 1.7 to 7.7 times faster than serial, with most of the speed‐up achieved by about 6 processor cores. Parallel speed‐up was generally greater on finer temporal meshes, while the initial guess strategy had minimal impact on speed‐up. Considerable speed‐up can be achieved for some optimal control simulation problems in OpenSim Moco by leveraging the multicore processors often available in modern computers. However, since improvements are problem specific, achieving optimal computational performance will require some degree of exploration by the end user. [ABSTRACT FROM AUTHOR]

This article presents a novel parallel path detection algorithm for identifying suspicious fraudulent accounts in large-scale banking transaction graphs. The proposed algorithm is based on a three-step approach that involves constructing a directed graph, shrinking strongly connected components, and using a parallel depth-first search algorithm to mark potentially fraudulent accounts. The algorithm is designed to fully exploit CPU resources and handle large-scale graphs with exponential growth. The performance of the algorithm is evaluated on various datasets and compared with serial time baselines. The results demonstrate that our approach achieves high performance and scalability on multi-core processors, making it a promising solution for detecting suspicious accounts and preventing money laundering schemes in the banking industry. Overall, our work contributes to the ongoing efforts to combat financial fraud and promote financial stability in the banking sector. [ABSTRACT FROM AUTHOR]

A three-dimensional Network-on-Chip (3D NoC) equips modern multicore processors with good scalability, a small area, and high performance using vertical through-silicon vias (TSV). However, the failure rate of TSV, which is higher than that of horizontal links, causes unpredictable topology variations and requires adaptive routing algorithms to select the available paths dynamically. Most works have aimed at the congestion control for TSV partially 3D NoCs to bypass the TSV reliability issue, while others have focused on the fault tolerance in TSV fully connected 3D NoCs and ignored the performance degradation. In order to adequately improve reliability and performance in TSV fully connected 3D NoC architectures, we propose a TSV-aware Reinforcement Learning Assisted Routing Algorithm (RLARA) for fault-tolerant 3D NoCs. The proposed method can take advantage of both the high throughput of fully connected TSVs and the cost-effective fault tolerance of partially connected TSVs using periodically updated TSV-aware Q table of reinforcement learning. RLARA makes the distributed routing decision with the lowest TSV utilization to avoid the overheating of the TSVs and mitigate the reliability problem. Furthermore, the K-means clustering algorithm is further adopted to compress the routing table of RLARA by exploiting the routing information similarity. To alleviate the inherent deadlock issue of adaptive routing algorithms, the link Q-value from reinforcement learning is combined with the router status based in buffer utilization to predict the congestion and enable RLARA to perform best even under a high traffic load. The experimental results of the ablation study on simulator Garnet 2.0 verify the effectiveness of our proposed RLARA under different fault models, which can perform better than the latest 3D NoC routing algorithms, with up to a 9.04% lower average delay and 8.58% higher successful delivered rate. [ABSTRACT FROM AUTHOR]

Summary: Asymmetric multicore processors (AMPs) couple high‐performance big cores and power‐efficient small ones, all exposing a shared instruction set architecture to software, but with different microarchitectural features. The energy efficiency benefits of AMPs, together with the general‐purpose nature of the various cores, have led hardware manufacturers to build commercial AMP‐based products, first for the mobile and embedded domains, and more recently, for the desktop market segment, as with the Intel Alder Lake processor family. This trend indicates that AMPs may become a solid and more energy efficient replacement for symmetric multicores in a wide range of application domains. Previous research has demonstrated that the system software can substantially improve scheduling—critical to get the most out of heterogeneous cores—by leveraging hardware facilities that are directly managed by the OS, such as performance monitoring counters, or the recently introduced Intel Thread Director technology. Unfortunately, the OS‐level support enabling access to these hardware facilities may often take a long time to be adopted in operating systems, or may come in forms that make its utilization challenging from specific levels of the system software stack, especially in production systems. To fill this gap, we propose PMCSched, an open‐source framework enabling rapid development and evaluation of custom scheduling‐related support in the Linux kernel. PMCSched greatly simplifies the design and implementation of a wide range of scheduling policies for multicore systems that operate at different system software layers without requiring to patch the kernel. To demonstrate the potential of our framework, we conduct a set of experimental case studies on asymmetry‐aware scheduling for Intel Alder Lake processors. [ABSTRACT FROM AUTHOR]