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Introduction: Radiotherapy is one of the important treatment modalities in cancer treatment. To maintain the treatment procedure accuracy, the phantom is an essential tool for absolute dosimetry conformation and Quality Assurance routine cheek up. This work aims to study the absorbed dose of various phantoms and hence to make a comparison of the result with the IAEA recommendation (TRS 398) for daily QA of Linac. Materials and Methods: The experiment has been done at the Institute of Nuclear Medical Physics (INMP), AERE, Savar, Dhaka, under the Bangladesh Atomic Energy Commission. For external beam radiation, 6 MV and 15 MV photon beams of Varian Clinac iX Linear Accelerator (Linac) were used. One dimensional (1D) water phantom, solid water phantom, and MatriXX with MULTICube phantom and associate accessories were used to experiment. Results: We have measured and compared the absorbed dose data of the phantoms. The variation of sold water phantom from the 1D water phantom is +2.8% at 6 MV and +3.5% at 15 MV. The variation MatriXX with MULTIcube phantom from the 1D water phantom is +8.0% at 6 MV and +3.2% at 15 MV. This study revealed that the 1D water phantom was the best absolute dose conformation among the other phantoms and the deviation was within the acceptable limit (±5%), except MatriXX with MULTICube Phantom for low energy beam (8%). Conclusion: It was observed that the accuracy of dose estimation was better in the 1D water phantom rather than the other two. It is also known that the 1D water phantom is low cost but needs a long time to set up for the experimental arrangement. Solid water or MatriXX with MULTICube phantom can be used to overcome this problem, which takes only a few minutes for setup and is comparatively faster than 1D water phantom.

We describe a novel type of retroreflector, which we call a “multicube” retroreflector, optimized to provide improved optical power return when a large number of retroreflectors are dispersed through a volume or on a surface. While it does not match the performance of a “multiplane cross” type retroreflector on an individual level, it offers improved performance compared to a standard corner cube while retaining the corner cube’s advantages: fabrication via stamping, and the ability to densely pack the retroreflectors. When dispersed as part of a cloud of retroreflectors, the multicube design provides significant performance improvements over both simple corner cubes and “multiplane cross” retroreflectors.

Editor's note :As embedded systems grow more complex and as new applications such as IoT require many design constraints, sophisticated design space exploration techniques are essential in order to find the best compromise between different design goals and their tradeoff. This tutorial gives a structured insight into the field of design space exploration for embedded systems.

To meet the ever shrinking time-to-market for multimedia embedded systems, designers need effective system-level optimization techniques to support their design decisions. Despite multimedia embedded systems' highly variable execution times and soft real-time constraints, most previous work has adopted a constant execution time (worst-case) approach to evaluate if a candidate architecture satisfies the timing constraints. Such an approach is too pessimistic and might result in unnecessary costly architectures. In this work, we propose a new method for design space exploration of multimedia embedded systems. Given a system specification, the proposed method automatically explores the design space to quickly identify Pareto-optimal solutions (or an approximation) that optimize conflicting design metrics, such as price and power consumption. Our approach combines (i) a fast and formal strategy for performance evaluation that captures the varying runtime behavior of multimedia systems and (ii) a new multi-objective genetic algorithm for architecture exploration. The experiments on well-known benchmarks show the efficiency of our method in comparison to similar ones.

In this paper we outline Design Space Exploration methodology aimed at homogeneous multi-core architectures, where the safety-criticality is the crux of a system design. Multi-core architectures provide better computational abilities, but at the same time complicate the computation of timing bounds. Determining suitable architectures that achieve timing requirements is an important aspect for a system designer. The proposed work conceptualizes ways to automate and explore different design facets of a multi-core processor. The intention is to ensure that the particular application meets its deadlines, while optimizing other objectives such as minimizing hardware costs, energy consumption and floor area. The automated exploration builds upon Mulitcore Response Time Analysis for timing verification and multicube for heuristic search methods. The aim is to generate an architecture design in the end that can be used directly to build a custom application specific processor.

The previous chapter concentrated on the design of the fault detection and diagnosis system based on SCC and ANN respectively; based on the extracted features described in Chap. 6. In this chapter the implementation of the proposed robot health monitoring system using an embedded system is discussed. A short overview of the currently available embedded systems for condition monitoring applications is provided, to evaluate their appropriateness for the work here. Then, a systematic methodology has been followed for the electronic hardware, which makes up the embedded monitoring system, selection process by investigating the available options in the market and suitability for this project. The configuration of several parameters of the developed embedded system is discussed and results presented, and the final system enclosure and installation described.

Aim To study the sensitivity of three commercial dosimetric systems, Delta4, Multicube and Octavius4D, in detecting Volumetric Modulated Arc Therapy (VMAT) delivery errors. Methods Fourteen prostate and head and neck (H&N) VMAT plans were considered for this study. Three types of errors were introduced into the original plans: gantry angle independent and dependent MLC errors, and gantry angle dependent dose errors. The dose matrix measured by each detector system for the no-error and error introduced delivery were compared with the reference Treatment Planning System (TPS) calculated dose matrix for no-error plans using gamma (γ) analysis with 2%/2 mm tolerance criteria. The ability of the detector system in identifying the minimum error in each scenario was assessed by analysing the gamma pass rates of no error delivery and error delivery using a Wilcoxon signed-rank test. The relative sensitivity of the system was assessed by determining the slope of the gamma pass line for studied error magnitude in each error scenario. Results In the gantry angle independent and dependent MLC error scenario the Delta4, Multicube and Octavius4D systems detected a minimum 2 mm error. In the gantry angle dependent dose error scenario all studied systems detected a minimum 3% and 2% error in prostate and H&N plans respectively. In the studied detector systems Multicube showed relatively less sensitivity to the errors in the majority of error scenarios. Conclusion The studied systems identified the same magnitude of minimum errors in all considered error scenarios.

An embedded system is a special-purpose computer system designed to perform one or a few dedicated functions often with real time computing constraints. It is usually embedded as part of a complete device including hardware and mechanical parts. In contrast, a general-purpose computer, such as a personal computer, can do many different tasks depending on programming. Embedded systems control many of the common devices in use today. Since the embedded system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product, or increasing the reliability and performance. Complexity varies from low, with a single microcontroller chip, to very high with multiple units, peripherals and networks mounted inside a large chassis or enclosure. In general, "embedded system" is not an exactly defined term, as many systems have some element of programmability. For example, Handheld computers share some elements with embedded systems — such as the operating systems and microprocessors which power them — but are not truly embedded systems, because they allow different applications to be loaded and peripherals to be connected. In this presentation we are going to concentrate on embedded systems, real-time operating systems, its classification, comparison with OS configuration and design process. The full text of the article is not available in the cache. Kindly refer the IJCA digital library at www.ijcaonline.org for the complete article. In case, you face problems while downloading the full-text, please send a mail to editor at editor@ijcaonline.org Kamlesh Radheshyam Tiwari T.E.Instrumentation D.N.Patel C.O.E, shahada

As embedded systems are getting popular in industrial product designs, a dedicated teaching laboratory for embedded systems (EST Lab) has been setup for college and graduate students to get familiar with embedded system engineering and researches. In this paper, we present our experiences in embedded system education curriculum and teaching laboratory design carried out in the past few years. Accompanied by a series of courses with hands-on exercises, students can understand the whole picture of embedded systems in a more systematic way. To give students a comprehensive view of embedded systems, the curriculum includes not only embedded hardware architectures and operating systems but also embedded user-level software designs. We select the most popular and available open-source operating system, Linux 2.6, as the primary experimental platform for all laboratory practices. In addition to the course design, several research results derived from this laboratory are also presented in this paper.

Reference metrics are used to define the differential structure on multicube representations of manifolds, i.e., they provide a simple and practical way to define what it means globally for tensor fields and their derivatives to be continuous. This paper introduces a general procedure for constructing reference metrics automatically on multicube representations of manifolds with arbitrary topologies. The method is tested here by constructing reference metrics for compact, orientable two-dimensional manifolds with genera between zero and five. These metrics are shown to satisfy the Gauss-Bonnet identity numerically to the level of truncation error (which converges toward zero as the numerical resolution is increased). These reference metrics can be made smoother and more uniform by evolving them with Ricci flow. This smoothing procedure is tested on the two-dimensional reference metrics constructed here. These smoothing evolutions (using volume-normalized Ricci flow with DeTurck gauge fixing) are all shown to produce reference metrics with constant scalar curvatures (at the level of numerical truncation error)., Comment: 37 pages, 16 figures; additional introductory material added in version accepted for publication

11 pp; International audience; This article deals with real-time embedded system design and verification. Real-time embedded systems are frequentlydesigned according to multi-tasking architectures that have timing constraints to meet. The design of real-time embeddedsystems expressed as a set of tasks raises a major challenge since designers have to decide how functions of the system mustbe assigned to tasks. Assigning each function to a different task will result in a high number of tasks, and then in higherpreemption overhead. In contrast, mapping many functions on a limited number of tasks leads to a less flexible design whichis more expensive to change when the functions of the system evolve. This article presents a method based on an optimizationtechnique to investigate the assignment of functions to tasks. We propose a multi-objective evolution strategy formulation whichboth minimizes the number of preemptions and maximizes task laxities. Our method allows designers to explore the search spaceof all possible function to task assignments and to find good tradeoffs between the two optimization objectives among schedulablesolutions. After explaining our mapping approach, we present a set of experiments which demonstrates its effectiveness fordifferent system sizes.

The presented Ph.D. work deals with the development of a framework to support the design of embedded systems. In particular, it focuses on the development of a unobtrusive profiling system to support, at run-time, both the definition of the best execution platform and its resource optimization. The final goal is the definition of a framework exploiting reconfigurable logic, based on monitoring actions and run-time decisions. The profiling system under development and its high portability toward different architectures, representing current status of Ph.D. work, are described. Planned future steps, including benchmarking by means of industrial applications, are illustrated.

Embedded systems are developed within a cost-driven process, such that many purpose-build systems share a common embedded platform. For instance, a shared hardware device might be applied in various use cases with different software. Here, the bare hardware is considered as platform while the final hardware/software system is the product that implements a certain set of features. In this paper, we propose an efficient design space exploration methodology that optimizes a set of embedded platforms. For this purpose, we separate the exploration into two stages: (1) A set of candidate platforms is determined within an optimization framework that can cope with different system models, considering the optimization objectives and feature coverage. (2) The final set of target platforms is determined as subset of the candidates by minimizing the expected objectives like cost, area, etc. The experimental results give evidence that our modular approach is more flexible and scalable than state-of-the-art methodologies.

Current embedded systems are increasingly used to support high-performance applications. This is due to the diffusion of these systems in the domain of mobile devices and the need of a large number of services required from these systems. To support the execution of these applications, several architectures based on CPU, GPU or FPGA have been developed and are still under investigation. When the application demands both performance and flexibility, architectures based on several types of execution resources are of high benefit. In this context, designers define architectures which include all the necessary resources on the same chip, also called ‘‘Multiprocessor System on a Chip’’ (MPSoC). Image processing is one of the major applications in embedded domain, which requires high effort in computation. Image processing for medicine, automotive, and for video compression is the main algorithm that has been addressed by the authors of the Design and Architecture for Image and Signal Processing (DASIP) conference. This special issue presents several papers which address this general topic, and also presents papers dealing with the implementation complexity as well as exploring different opportunities concerning the possible architectures of CPU, GPGPU, FPGA and ASIC implementations. Comparisons among these different technologies are also presented in order to attempt defining the best implementation of the applications. Due to the complexities of the applications and architectures, research concerning methodologies for implementation is also addressed in this special issue. The main objective is to provide designers efficient methodologies and tools which can help during the exploration of different implementation opportunities. In the next paragraph, the guest editors provide a brief description of each paper presented in this special issue. We wish to have provided JRTIP readers a good reading collection and hope that these selected papers will be a source of inspiration for future works.

Embedded systems (ES) are a special-purpose computer system designed to perform one or few dedicated functions. The development of embedded system is getting difficult due to the short life-cycle of the embedded products and high complexity of embedded systems design. In this chapter, we analyze a possible method to design Embedded Systems.

Embedded software and electronics are major contributors of values in vehicles, and play a dominant role in vehicle innovations. The design of automotive embedded systems has become more and more challenging, with the rapid increase of system complexity and more requirements on various design objectives. Methodologies such as model-based design are being adopted to improve design quality and productivity through the usage of functional models. However, there is still a significant lack of design automation tools, in particular synthesis and optimization tools, that can turn complex functional specifications to correct and optimal software implementations on distributed embedded platforms. In this paper, we discuss some of the major technical challenges and the problems to be solved in automotive embedded systems design, especially for the synthesis and optimization of embedded software.

We present a technique for automatic exploration of architectural alternatives in the design of complex electronic embedded systems and systems-on-a-chip. The technique transforms the problem into a set of simple model-to-model operations and a mapping algorithm that becomes the core of the entire design process. The mapping algorithm is formulated as an assignment-type problem (ATP), which is, in turn, solved by a straightforward optimization method. The result is a design assistance tool, which is demonstrated through a telecommunication systems example.

The complexity of the design problem becomes apparent when considering the huge design space of possible implementations on the one hand and the many conflicting design goals on the other. Automated design tools are necessary in order to handle the complexity of today's systems and to support the designer in finding the trade-off that best fits the market requirements. This article presents a methodology to cope with the simultaneous optimization of multiple competing objectives and the different sources of heterogeneity in embedded system design.

In the development of embedded systems, co-simulation permits the systematic exploration of the design space with the aim of selecting models of optimal solutions, and allowing trade-offs between computing and physical elements of alternative designs. We present an approach to such design space exploration using experiment design. Beginning from a classification for the parameters that one may wish to vary during an experiment, we discuss methods for reducing the number of experiments performed, from screening experiments to the use of orthogonal matrices or a space-filling search. Two case studies which illustrate the importance of careful experiment design in this context. We finally discuss ways in which experimental results may be ranked to permit automatic selection of the best designs analysed.

An iterative mean value analysis (MVA) algorithm is developed in this paper for a class of queueing networks (QNs) with forking (MVAF). The algorithmic development is motivated by the performance evaluation of a Multicube multiprocessor system and its cache coherent protocol proposed by Goodman and Woest, 1988. We model the system as a multichain, multiclass, mixed QN with forking phenomena. The MVAF algorithm that we propose approximates a forking by independent flows at each iteration and iteratively applies MVA to the approximate QNs without forking. We prove that MVAF converges to the exact performance measures for the QN with forking. Comparisons among performance evaluations by MVAF, simulation and the mean value performance analysis by Leutennegger and Vernon, 1988, demonstrate both the validity and effectiveness of MVAF.

It is widely understood that the next revolution of virtual platform-based design is the holistic optimization of hardware parameters, task mapping and scheduling, and application tuning for many-cores. As a community, we have learned that finding the best trade-off in terms of selected figures of merit can be achieved only by considering the integrated hardware and software dimensions, by evaluating an enormous number of configurations, each characterized by a long simulation time. The problem worsens when dealing with small ecosystems such as embedded systems-on-chip where the environment is too constrained to assume that a sophisticated run-time algorithm can be implemented to schedule efficiently the access to resources. In this keynote I will explain why some newest findings in global optimization can be used to address effectively virtual-platform design. I am going then to describe how sophisticated algorithms based on response-surface prediction models can efficiently identify optimal configurations in a significant number of platform optimization scenarios. Finally, I am going to outline some research directions stemming from the MULTICUBE and 2PARMA EU projects that I think will untap the full potential of platform optimization.

The ENOSYS project, funded by the EC, aims to shorten the time-to-market of high-performance SoCs by providing design and tool flows for the design and the implementation of embedded systems by seamless integration of high-level system specifications, software code generation, hardware synthesis, code optimization and design space exploration. The objective here is to automatically generate code, for implementation in execution platforms such as FPGAs, from validated high level designs incorporating initial end user requirements, system functional and non-functional description, platform modelling. This paper describes the design flow developed in the context of the ENOSYS project and the results of a first industrial evaluation through two industrial test cases.

Multi-Objective Evolutionary Algorithms (MOEAs) have received increasing interest in industry, because they have proved to be powerful optimizers. Despite the great success achieved, MOEAs have also encountered many challenges in real-world applications. One of the main difficulties in applying MOEAs is the large number of fitness evaluations (objective calculations) that are often needed before a well acceptable solution can be found. In fact, there are several industrial situations in which both fitness evaluations are computationally expensive and, meanwhile, time available is very low. In this applications efficient strategies to approximate the fitness function have to be adopted, looking for a trade-off between optimization performances and efficiency. This is the case of a complex embedded system design, where it is needed to define an optimal architecture in relation to certain performance indexes respecting strict time-to-market constraints. This activity, known as Design Space Exploration DSE), is still a great challenge for the EDA (Electronic Design Automation) community. One of the most important bottleneck in the overall design flow of a embedded system is due to the simulation. Simulation occurs at every phase of the design flow and it is used to evaluate a system candidate to be implemented. In this chapter we focus on system level design proposing a hybrid computational intelligence approach based on fuzzy approximation to speed up the evaluation of a candidate system. The methodology is applied to a real case study: optimization of the performance and power consumption of an embedded architecture based on a Very Long Instruction Word (VLIW) microprocessor in a mobile multimedia application domain. The results, carried out on a multimedia benchmark suite, are compared, in terms of both performance and efficiency, with other MOGAs strategies to demonstrate the scalability and the accuracy of the proposed approach.

System level modeling and design space exploration has an important role in Multi processor embedded system on chip design. Y-chart modeling is a well-known method for solving design space exploration problem. One of the most important stages in Y-chart approach is mapping an application onto architecture. In this paper, MOPSO algorithm has been proposed to obtain optimized solutions for mapping. The proposed method is tested using the MJPEG application as a case study in terms of accuracy and efficiency. Simulation results show that proposed algorithm will provide the designer with accurate solutions with a considerable reduction in design time. Finally a number of multi objective optimization results are simulated and verified by the Sesame framework.

For pre-treatment plan verification of advanced treatment techniques such as intensity-modulated arc therapy, a fast and reliable dosimetric device is required. In this study, we investigated the suitability of MatriXX in different setups for verification of volumetric modulated arc therapy (VMAT) plans. If MatriXX is used in a stationary phantom (MULTICube), the measured dose is dependent on the beam angle. For the first setup (MatriXX/MULTICube), we developed correction factors (CFs) for each detector element (1020 CFs). We investigated the accuracy of these CFs by verifying 12 VMAT plans. In the second setup, we also assessed the suitability of MatriXX in a dedicated holder. Using this setup (MatriXX/Holder), 30 additional VMAT plans were verified. Deviations of up to ∼17% and ∼11% were noted for one of the ion chambers at 90° and 180° gantry positions. The influence of the beam angle dependence (MULTICube) can explicitly be seen when a gamma criterion of 2%/2 mm was chosen. An overall improvement of 4.3% of passing pixels (pp) was noted after applying beam angular-dependent CFs. When the gamma criterion was 3%/3 mm, the %pp was ≥ 95% without and ∼100% with correction. With the second setup, MatriXX/holder, we showed excellent agreement between measurements and calculations. The %pp averaged over all plans (30 VMAT treatment plans) was nearly ∼100%. The combination of MatriXX with MULTICube or with holder proved to be a fast and reliable method for pretreatment verification of arc therapy with sufficient accuracy.

This chapter will present the application of MULTICUBE methodology to the design of a ITU G.hn compatible component for powerline communication. Powerline communication is an advanced telecommunication system allowing fast and reliable transfer of audio, video and data information using the most ubiquitous transmission system: the power lines. This transmission line is used to exchange information between different equipment connected to the network using the advanced coding techniques like such as Orthogonal Frequency Division Multiplexing. The starting point of the analysis is a high level SystemC-based virtual platform where we will study the effect of the variation of a pre-defined set of design parameters on a set of pre-defined metrics. This automatic analysis will drive the design choices in order to build an optimized industrial system.We will show that the SystemC-based virtual platform combined with the MULTICUBE design space exploration framework can save up to 80% of designer work time while achieving better results in terms of performance.

This chapter introduces the design-flow of the MULTICUBE project whose main goal is the definition of an automatic multi-objective Design Space Exploration (DSE) framework to be used to tune the parameters of System-on-Chip architectures by taking into account the target set of metrics (e.g. energy, latency, throughput, etc.). One of the important goals of the automatic multi-objective DSE framework is to find design trade-offs that best meet system constraints and cost criteria which are indeed strongly dependent on the target application.A set of heuristic optimisation algorithms have been defined to reduce the overall optimization time by identifying an approximated Pareto set of parameter configurations with respect to a set of selected figures of merit. Once the approximated Pareto set is built, the designer can quickly apply decision criteria to select the best configuration satisfying the constraints. The DSE flow is based on the interaction of two frameworks to be used at design time: the Design Space Exploration Framework, a set of opensource and proprietary architectural exploration tools, and the Power/Performance Estimation Framework, a set of modeling and simulation tools (open-source and proprietary) operating at several levels of abstraction. The DSE flow also includes the specification of an XML integration interface to connect the exploration and estimation frameworks and a Run-time Resource Manager exploiting, at run-time, the best software configuration alternatives derived at design-time to optimize the usage of system resources.

This chapter will present two significant applications of the MULTICUBE design space exploration framework. The first part will present the design space exploration of a low power processor developed by STMicroelectronics by using the modeFRONTIER tool to demonstrate the benefits DSE not only in terms of objective quality, but also in terms of impact on the design process within the corporate environment. The second part will describe the application of RSM models developed within MULTICUBE to a tiled, multiple-instruction, many-core architecture developed by ICT China. Overall, the results have showed that different models can present a trade-off of accuracy versus computational effort. In fact, throughout the evaluation, we observed that high accuracy models require high computational time (for both model construction time and prediction time); vice-versa low model construction and prediction time has led to low accuracy.

Technology trends enable the integration of many processor cores in a System-on-Chip (SoC). In these complex architectures, several architectural parameters can be tuned to find the best trade-off in terms of multiple metrics such as energy and delay. The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.

This chapter is dedicated to the optimization algorithms developed in the MULTICUBE project and to their surrounding environment. Two software design space exploration (DSE) tools host the algorithms: Multicube Explorer and mode-FRONTIER. The description of the proposed algorithms is the central part of the chapter. The focus will be on newly developed algorithms and on ad-hoc extensions of existing techniques in order to face with discrete and categorical design space parameters that are very common when working with embedded systems design. This chapter will also provide some fundamental guidelines to build a strategy for testing the performance and accuracy of such algorithms. The aim is mainly to build confidence in optimization techniques, rather than to simply compare one algorithm versus another one. The “no-free-lunch theorem for optimization” has to be taken into consideration and therefore the analysis will look forward to robustness and industrial reliability of the results.

Computer-aided design has been traditionally applied to computers and embedded systems but not to the communication infrastructure among them. The paper contributes to fill this gap by proposing to use a mathematical language to model a distributed application in terms of tasks, hosting nodes, and interactions with the environment. Tasks are described in terms of computation and communication requirements also in relationship with state-of-the-art languages for system specification. Entities and relationships are introduced to relate tasks, data flows and environmental data to network nodes, channels among them and communication protocols. The resulting attributes and constraints can be used during a further designspace exploration to synthesize automatically a suitable communication infrastructure. The approach can be applied to significant applications, e.g., those based on wireless sensor networks and peer-to-peer networks. An example related to building automation is also reported to demonstrate the potentiality of the framework.

Modern embedded systems have increased their functionality by using a large amount and diversity of hardware and software components. Realizing the expected system functionality is a complex task. Such complexity must be managed in order to decrease time-to-market and increase system quality. This chapter presents a method for high-level design space exploration (DSE) of embedded systems that uses model-driven engineering (MDE) and aspect-oriented design (AOD) approaches. The modelling style and the abstraction level open new design automation and optimization opportunities, thus improving the overall results. Furthermore, the proposed method achieves better reusability, complexity management, and design automation by exploiting both MDE and AOD approaches. Preliminary results regarding the use of the proposed method are presented.

This tutorial discusses design space exploration and software automation based on an UML front-end. First, we review software automation tools targeted at the embedded systems domain. Following, we present an approach for the estimation of memory, performance, and energy of a given application modeled from an initial UML specification. We proceed with an analysis of the possibilities of linking different modeling environments for software generation (Simulink and UML, for example). Finally, we show the possibilities of using other specification languages to obtain more abstraction and allow design space exploration together with software automation.

In this paper we present a multi-objective genetic algorithm to solve the problem of mapping a set of task graphs onto a heterogeneous multiprocessor platform. The objective is to meet all real-time deadlines subject to minimizing system cost and power consumption, while staying within bounds on local memory sizes and interface buffer sizes. Our approach allows for mapping onto a fixed platform or onto a flexible platform where architectural changes are explored during the mapping.

System level design incorporating system modeling and formal specification in combination with formal verification can substantially contribute to the correctness and quality of the embedded systems and consequently help reduce the development costs. Ensuring the correctness of the designed system is, of course, a crucial design criterion especially when complex distributed (realtime) embedded systems are considered. Therefore, this paper aims at presenting a verification framework designated for formal verification and validation of UML-based design of embedded systems. It first introduces an approach of using the AsmL language for acquiring formal models of the UML semantics and consequently presents an on-the-fly model checking technique designed to run the formal verification directly over those semantic models.

Embedded systems are everywhere: from alarm clocks to PDAs, from mobile phones to cars, almost all the devices we use are controlled by embedded systems. Over 99% of the microprocessors produced today are used in embedded systems, and recently the number of embedded systems in use has become larger than the number of humans on the planet.

Verification and validation consists in exploring the current design against side properties expressed as part of the requirements. Verification & validation can concern: 1. the specification level, at early stages of the design process, or 2. the embedded code, from C/Ada/Java, to assembly.

In this paper we present the intra-function dynamic estimation step of our system-level design space exploration tool. The aim of our global methodology is to fill the gap between system specification and the tasks of the system design flow to converge towards an efficient system on chip architecture for multimedia applications. In this context, the intra-function estimation step rapidly provides for each functional block of the specification, trade-off curves which represent a large set of parallelism options for both data-transfer and processing resources. A set of methods used to achieve this estimation process is detailed.

Automatic embedded software generation and IP-based design are good approaches to achieve a short design cycle due to stringent time-to-market requirements. But design automation must also consider application-specific requirements. This paper presents a mechanism for the automatic selection of software IP components for embedded applications, which is based on a software IP library and a design space exploration tool. The software IP library has different algorithmic implementations of several routines commonly found in different application domains. These routines have been characterized in terms of power, performance, and area, for a given architectural platform. The design exploration tool allows the automatic configuration of an optimized solution for a specific application, by selecting routines whose combination best match system requirements. Experimental results are presented and demonstrate that a very expressive design space can be explored with this approach.

Several features such as reconfiguration, voltage and frequency scaling, low-power operating states, duty-cycling, etc. are exploited for latency and energy efficient application design using heterogeneous embedded systems. However, more choices during application design results in a large design space that must be traversed efficiently. In this paper, we propose a hierarchical methodology that integrates optimization heuristics, high-level performance estimators, and low-level simulators to enable efficient exploration of large design spaces. Our methodology is fast, robust against approximation errors due to high-level modeling, and can evaluate a much larger design space than an optimization heuristic only design space exploration technique. We have augmented MILAN, a model-based integrated simulation framework for embedded systems, to develop an environment to perform hierarchical design space exploration. Using our methodology for a beamforming application, we identify an energy-efficient mapping onto a heterogeneous embedded system while meeting a given latency constraint. We also demonstrate the use of our methodology in identifying an energy and latency efficient heterogeneous embedded system based on user-specified performance requirements for a personnel detection algorithm from a set of devices that includes FPGAs, DSPs, and traditional processors.

This paper describes the architecture of fault tolerant pipeline processors. It uses multicube interconnection and voting based on cell reliability. Our architecture, featuring majority voting of results and reliability assessment to cells, ensures higher performance over conventional approaches in fault tolerance. >

We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simulation, which tend to be infeasible when the design space is very large. We illustrate the feasibility of our method using a detailed case study.