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In managing enterprise, uncertainty belongs to the attributes of the decision making processes. In competitive environments, where success depends on high-quality decisions, taking the wrong steps can lead to loss of market share or even contribute to running out of business. That is why it is important to choose from the many alternatives those methods which will be most effective in solving problems in a simple and quick way, and heuristics offer such a solution, which has proved its usefulness in uncertain business environments. The aim of this study is to present and evaluate heuristic methods and show their specificity and applicability in management science for enterprises in times of uncertainty. In this article, the theoretical aspect of managerial heuristics is presented, and the emphasis is also placed on presenting practical examples of applying heuristics in companies with times of uncertainty, but also in these times of the Covid-19 pandemic. The study also offers conclusions and provides practi al recommendations.

The main purpose of the method proposed in this article is to reduce the number of look-up-table (LUT) elements in logic circuits of sequential devices. The devices are represented by models of Mealy finite state machines (FSMs). Thesee are so-called MPY FSMs based on two methods of structural decomposition (the replacement of inputs and encoding of output collections). The main idea is to use two types of state codes for implementing systems of partial Boolean functions. Some functions are based on maximum binary codes; other functions depend on extended state codes. The reduction in LUT counts is based on using the method of twofold state assignment. The proposed method makes it possible to obtain FPGA-based FSM circuits with four logic levels. Only one LUT is required to implement the circuit corresponding to any partial function. An example of FSM synthesis using the proposed method is shown. The results of the conducted experiments show that the proposed approach produces LUT-based FSM circuits with better area-temporal characteristics than for circuits produced using such methods as Auto and One-hot of Vivado, JEDI, and MPY FSMs. Compared to MPY FSMs, the values of LUT counts are improved. On average, this improvement is 8.98%, but the gain reaches 13.65% for fairly complex FSMs. The maximum operating frequency is slightly improved as compared with the circuits of MPY FSMs (up to 0.64%). For both LUT counts and frequency, the gain increases together with the growth for the numbers of FSM inputs, outputs and states.

A method is proposed that is focused on reducing the chip area occupied by logic elements creating the circuit of Mealy finite state machines (FSMs). The proposed method is aimed at FSM circuits implemented with internal resources of field-programmable gate arrays (FPGA). The required chip area is estimated by the number of look-up table (LUT) elements in a particular circuit. The method is based on mutual application of two methods of structural decomposition. The first of them is based on dividing the set of outputs and using unitary-maximum encoding of collections of FSM outputs. The second method is based on dividing the set of states by classes of compatible states. The optimization is achieved by replacing the maximum binary state codes by two-part codes proposed in this article. Each two-part state code consists of a code of a class including a particular state and a maximum binary code of this state inside a particular class. The proposed approach leads to three-level LUT-based Mealy FSM circuits. The first logic level generates three types of partial functions: unitary encoded outputs, variables encoding collections of outputs, and input memory functions. Each partial function is represented by a circuit including a single LUT. The LUTs from the second logic level generate final values of these functions. The LUTs from the third level implement outputs using collections of outputs. An example of synthesis applying the proposed method is discussed. The experiments were conducted using standard benchmark FSMs. Their results showed significant improving of the area occupied by an FSM circuit. The LUT count decreased on average by 9.49%. The positive side effect of the proposed method was increasing the value of the maximum operating frequency (on average, by 8.73%). The proposed method is advisable to use if a single-level LUT-based implementation of the FSM circuit is impossible.

A method is proposed targeting implementation of FPGA-based Mealy finite state machines. The main goal of the method is a reduction for the number of look-up table (LUT) elements and their levels in FSM logic circuits. To do it, it is necessary to eliminate the direct dependence of input memory functions and FSM output functions on FSM inputs and state variables. The method is based on encoding of the terms corresponding to rows of direct structure tables. In such an approach, only terms depend on FSM inputs and state variables. Other functions depend on variables representing terms. The method belongs to the group of the methods of structural decomposition. The set of terms is divided by classes such that each class corresponds to a single-level LUT-based circuit. An embedded memory block (EMB) generates codes of both classes and terms as elements of these classes. The mutual using LUTs and EMB allows diminishing chip area occupied by FSM circuit (as compared to its LUT-based counterpart). The simple sequential algorithm is proposed for finding the partition of the set of terms by a determined number of classes. The method is based on representation of an FSM by a state transition table. However, it can be used for any known form of FSM specification. The example of synthesis is shown. The efficiency of the proposed method was investigated using a library of standard benchmarks. We compared the proposed with some other known design methods. The investigations show that the proposed method gives better results than other discussed methods. It allows the obtaining of FSM circuits with three levels of logic and regular interconnections.

A method is proposed for hardware reduction in FPGA-based Moore FSMs. The method is based on encoding of microoperations. An FSM circuit is implemented using a single EMB and LUTs. The example of synthesis is given.

The chapter is devoted to programmable logic controllers (PLC). We start from the classification of PLC, their architecture and cycle of operation. Next, the main laws of Boolean algebra are shown. We show the connection between the Boolean algebra and basic logic functions used in programming of PLC. Next, different programming languages used for PLC are shown. The last part is devoted to examples of programming for different Boolean functions and simple control algorithms. All programs are written using the Ladder Diagram language.

The chapter presents some methods using for implementing computational algorithms in embedded systems. All methods are illustrated using the same end-to-end example. We start from the hardware implementation when some operational units (adders, multipliers, and other) are used to implement an algorithm during a single cycle of operation. Next, we discuss how to minimize hardware due to introducing an internal control unit. The third section is devoted to software implementation of computational algorithms based on microcontrollers. Some families of microcontrollers are analysed. Next, we show how to choose blocks for implementing the embedded system for our example. We choose the microcontrollers ATmega32 to illustrate this implementation of the embedded system. At last, the heterogeneous implementation of computational algorithms is discussed. It is based on well-know conception of hardware-software co-design. We introduce the conception of hardware-software interface and show how to create an algorithm of its operation.

The automatic detection of nuclei within cytological samples is crucial for quantitative analysis in medical applications. Fortunately, modern digital microscopy systems allow imaging of biological material with very high accuracy. A typical cytological sample contains hundreds or thousands of cell nuclei that need to be examined for a particular type of cancer (or the exclusion of neoplastic lesions). Typically, this assessment is made by a qualified physician by visually analyzing a biological material. As the complexity of cellular structures is very high, automating this process is a big challenge. In this paper, we try to face this problem. Real cytological images of breast cancer patients were collected by pathologists from the University Hospital in Zielona Gora, Poland. The individual cell nuclei were automatically detected within cytological sample imagery. Then a couple of different shape and texture features were collected. Based on this data, an attempt was made to classify them in the context of the possibility of automatically identifying the type of cancer (malignant, benign). The results obtained are moderately promising.

This chapter provides some basic issues connected with embedded systems. Two types of computer systems are discussed (visible and invisible to a user). Next some example is shown allowing understanding the basic features of embedded systems. The common features of embedded systems and their characteristics are discussed. The final section is devoted to basic requirements to embedded systems.

The chapter is devoted with FPGA-based implementing control algorithms represented using the language of graph-schemes of algorithms. We use models of Mealy and Moore finite state machines (FSM) to design the circuits of control units. We start from single-level FSM circuits implemented using look-up table (LUT) elements and/or embedded memory blocks (EMB). These methods are illustrated using standard benchmark FSMs. Next, the methods of structural decomposition are discussed. We discuss how to reduce hardware using the replacement of logical conditions, encoding the collections of microoperations, encoding the terms, and transformation of objects. We show how to use the pseudoequivalent states for optimization of logic circuits of Moore FSMs. The third section is devoted to hardware reduction of Moore FSMs targeting the replacement of logical conditions. At last, we discuss how to optimize hardware replacing state registers by state counters. The discussed methods target control units based on models of Moore FSMs.

The chapter is devoted to different design methodologies targeting complex embedded systems. The hierarchy of levels is introduced, as well as Y-Chart proposed by Prof. Daniel Gajski. Using the Y-Chart, some basic methodologies are discussed such as bottom-up, top-down and meet-in-the middle. The third section is devoted to platform-based design of embedded systems. Next, the peculiarities of ASIC-based design are discussed. The last section is devoted to very important problem of increasing the energy efficiency of embedded systems.

The chapter deals with field-programmable gate arrays (FPGA). The basic stages are shown concerning evolution of programmable logic (from PROMs and PLAs to FPGAs). Next, the evolution of FPGAs is analysed. Three ages of FPGAs are shown. Next, the modern FPGAs produced by Xilinx and Intel (Altera) The last section is devoted to design methods targeting FPGAs. Basing on this information, we show how to execute calculations using digital signal processors, embedded memory blocks, and some components of Zynq 7000 by Xilinx.

A method is proposed for hardware reduction in FPGA-based Mealy FSMs. The method is based on encoding of the terms corresponding to rows of FSM direct structure table. The example of synthesis is given. The application of this method allows reducing the numbers of LUTs in FSM circuits.