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We consider factor-graph-based soft self-iterative equalization in wireless multipath channels. Since factor graphs are able to characterize multipath channels to per-path level, the corresponding soft self-iterative equalizer possesses reduced computational complexity in sparse multipath channels. The performance of the considered self-iterative equalizer is analyzed in both single-antenna and multiple-antenna multipath channels. When factor graphs of multipath channels have no cycles or mild cycle conditions, the considered self-iterative equalizer can converge to optimum performance after a few iterations; but it may suffer local convergence in channels with severe cycle conditions.

We consider coded multiple-input-multiple-output (MIMO) systems in block-fading channels employing iterative receivers, where the MIMO channels are scrambled by unitary matrices. We show that the unitary scrambling improves the outage performance with discrete input when the outer code rate is high, i.e., Ro > 0.5. We also demonstrate that the performance improvement from scrambling can be achieved by a small number of random unitary matrices. Moreover, with unitary scrambling, the signal model can be simplified, and the performance of the MIMO demodulator can be characterized by the singular values of the channel matrix. We then consider the design of irregular repeat-accumulate (IRA) codes for unitary scrambled MIMO block-fading channels. We propose a code design method by optimizing the IRA codes for EXtrinsic Information Transfer (EXIT) average with a given effective mutual information. We also propose a pessimistic code design for some system settings to improve the frame error rate performance. Index Terms--Block fading, code design, irregular repeat-accumulate (IRA) code, multiple-input-multiple-output (MIMO), outage analysis, unitary scrambling.

We treat the problem of designing low-density parity-check (LDPC) codes to approach the capacity of relay channels. We consider an efficient analysis framework that decouples the factor graph (FG) of a B-block transmission into successive partial FGs, each of which denotes a two-block transmission. We develop design methods to find the optimum code ensemble for the partial FG. In particular, we formulate the relay operations and the destination operations as equivalent virtual MISO and MIMO systems, and employ a binary symmetric channel (BSC) model for the relay node output. For AWGN channels, we further develop a Gaussian approximation for the detector output at the destination node. Jointly treating the relay and the destination, we analyze the performance of the LDPC-coded relay system using the extrinsic mutual information transfer (EXIT) chart technique. Furthermore, differential evolution is employed to search for the optimum code ensemble. Our results show that the optimized codes always outperform the regular LDPC codes with a significant gain; in the AWGN case, when Protocol-II is employed and the relay is close to the source, the optimized code performs within 0.1dB to the capacity bound. Index Terms--Cooperative relay channel, LDPC code, EXIT chart, factor graph.

We consider the design of efficient rate-compatible (RC) irregular repeat accumulate (IRA) codes over a wide code rate range. The goal is to provide a family of RC codes to achieve lfigh throughput in hybrid automatic repeat request (ARQ) scheme for high-speed data packet wireless systems. As a subclass of low-density parity-check codes, IRA codes have an extremely simple encoder and a low-complexity decoder while providing capacity approaching performance. We focus on a hybrid design method which employs both puncturing and extending. We propose a simple puncturing method based on minimizing the maximal recoverable step of the punctured nodes. We also propose a new extending scheme for IRA codes by introducing the degree-1 parity bits for the lower rate codes and obtaining the optimal proportions of extended nodes through density evolution analysis. The throughput performance of the designed RC-IRA codes in hybrid ARQ is evaluated for both AWGN and block fading channels. Simulation results demonstrate that our designed RC codes offer good error correction performance over a wide rate range and provide high throughput, especially in the high and low signal-to-noise ratio regions. Index Terms--Extending, hybrid automatic repeat request (ARQ), irregular repeat accumulate (IRA) codes, low-density parity-check (LDPC) codes, puncturing, rate compatible (RC).

This paper is concerned with the design consideration, fabrication process, and performance of a V-band monolithic transmit/receive (T/R) switch for millimeter-wave wireless networks applications. The developed switch integrated circuit (IC) has a novel structure in which to pass a signal, it presents a parallel resonant circuit to the signal by forward biasing a pair of switching heterojunction FET's (HJFET's), but to block the signal, it presents a series resonant circuit to the signal by reverse biasing the switching HJFET's. With a control voltage of 0/3.2 V, the developed T/R switch exhibits a minimum insertion loss of 3.9 dB, a maximum isolation of 41 dB, and a high switching speed of 250 ps, over 57-61 GHz. The monolithic T/R switch chip size is 3.3 mm x 1.7 mm.

This paper deals with the design considerations, fabrication process, and performance of coplanar waveguide (CPW) heterojunction FET (HJFET) down- and up-converter monolithic microwave integrated circuits (MMIC's) for V-band wireless system applications. To realize a mixer featuring a simple structure with inherently isolated ports, and yet permitting independent port matching and low local oscillator (LO) power operation, a 'source-injection' concept is utilized by treating the HJFET as a three-port device in which the LO signal is injected through the source terminal, the RF (or IF) signal through the gate terminal, and the IF (or RF) signal is extracted from the drain terminal. The down-converter chip incorporates an image-rejection filter and a source-injection mixer. The up-converter chip incorporates a source-injection mixer and an output RF filter. With an LO power and frequency of 7 dBm and 60.4 GHz, both converters can operate at any IF frequency within 0.5-2 GHz, with a corresponding conversion gain within -7 to -12 dB, primarily dominated by the related filter's insertion loss. Chip size is 3.3 mmx2 mm for the down-converter, and 3.5 mm x 1.8 mm for the up-converter.

This paper presents a 60-GHz-band GaAs heterojunction FET (HJFET) low-noise amplifier (LNA) operating with a single bias supply. A diode-regulated self-bias circuit was incorporated for suppressing the FET drain-current variations due to threshold voltage nonuniformities. The effect of the bias circuit on the drain - current distribution is carefully discussed based on the FET dc characteristics. A developed three-stage monolithic microwave integrated circuit (MMIC) LNA exhibited an average noise figure of 3.3 dB with 18-dB gain from 58 to 62 GHz. The LNA could operate over 2-5 V with a constant noise figure. The LNA chip size is 1.85 mm x 1.07 mm. Index Terms - Amplifier noise, millimeter-wave amplifiers, millimeter-wave integrated circuits, MMIC's, MODFET amplifiers.

This paper is concerned with the design considerations and performance results for low-voltage Si monolithic microwave/millimeter-wave integrated circuits (MMIC's) developed for mobile and personal communications applications. A 0.4 [[micro]meter] ECL-BiCMOS process technology was employed to develop bipolar-based RF amplifiers, MOS-based IF amplifiers, BiCMOS-based simplified Gilbert mixers, and monolithic downconverter as well as upconverter IC's incorporating these elements. These converters are designed to operate at a bias voltage of 2 V over 1.8-6.2 GHz exhibiting a conversion gain of 35-15 dB with a variable IF frequency of up to several 100 MHz. Chip size for both the downconverter and upconverter IC's is 1.0 mm x 0.7 mm.

We report on a high power, high efficiency, and small-size monolithic coplanar waveguide oscillator incorporating a single-stage buffer amplifier on the same chip. For the oscillator design, by changing RF current level through the device, the optimum load line was chosen in order to have an oscillation frequency insensitive to the effect of the subsequently connected amplifier, based on a device-circuit interaction concept. The amplifier, on the other hand, which was driven directly by the oscillator, was designed to achieve an overall high power and high efficiency operation. At 21 GHz, the output power of the developed chip recorded 17 dBm with an overall dc-RF efficiency of 22%. By changing the length of a source feedback line, the oscillation frequency was varied from 21 GHz to 26 GHz. For all cases, the output power remained higher than 16 dBm.

We consider factor-graph-based soft self-iterative equalization in wireless multipath channels. Since factor graphs are able to characterize multipath channels to per-path level, the corresponding soft self-iterative equalizer possesses reduced computational complexity in sparse multipath channels. The performance of the considered self-iterative equalizer is analyzed in both single-antenna and multiple-antenna multipath channels. When factor graphs of multipath channels have no cycles or mild cycle conditions, the considered self-iterative equalizer can converge to optimum performance after a few iterations; but it may suffer local convergence in channels with severe cycle conditions.

A quarter-wavelength diversity patch configuration for the 2.4-GHz ISM band PC card application is reported. The structure is based on partly interdigitation of two quarter wavelength separated patches through a set of fingers for achieving the required space diversity on single side printed substrate with an easy matching on 50 [Omega], high cross polarization and within a given maximum space of 30 mm x 50 min. Measured antenna patterns for a developed structure are the same as for a classical patch and the bandwidth for a VSWR less than two is 2% with a maximum gain of 1.5 dB. This antenna has been incorporated in a high-speed wireless LAN PC card system. Index Terms - Microstrip antennas.