94 results on '"Maged M. Michael"'
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2. A Practical, Scalable, Relaxed Priority Queue.
3. Quantitative comparison of hardware transactional memory for Blue Gene/Q, zEnterprise EC12, Intel Core, and POWER8.
4. PLDI 2004: Scalable Lock-Free Dynamic Memory Allocation.
5. Software Support and Evaluation of Hardware Transactional Memory on Blue Gene/Q.
6. Robust architectural support for transactional memory in the power architecture.
7. Evaluation of blue Gene/Q hardware support for transactional memories.
8. Laws of order: expensive synchronization in concurrent algorithms cannot be eliminated.
9. A Case for Including Transactions in OpenMP.
10. Real Java applications in software transactional memory.
11. Lock elision for read-only critical sections in Java.
12. Idempotent work stealing.
13. Reducing Memory Ordering Overheads in Software Transactional Memory.
14. Implementing and Exploiting Inevitability in Software Transactional Memory.
15. RingSTM: scalable transactions with a single atomic instruction.
16. Scale-up x Scale-out: A Case Study using Nutch/Lucene.
17. A theory of memory models.
18. Experiences Understanding Performance in a Commercial Scale-Out Environment.
19. Why the grass may not be greener on the other side: a comparison of locking vs. transactional memory.
20. Scalability of the Nutch search engine.
21. Practical Lock-Free and Wait-Free LL/SC/VL Implementations Using 64-Bit CAS.
22. Scalable lock-free dynamic memory allocation.
23. CAS-Based Lock-Free Algorithm for Shared Deques.
24. The balancing act of choosing nonblocking features.
25. Safe memory reclamation for dynamic lock-free objects using atomic reads and writes.
26. High performance dynamic lock-free hash tables and list-based sets.
27. High-Throughput Coherence Controllers.
28. Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors.
29. Why the grass may not be greener on the other side: a comparison of locking vs. transactional memory.
30. Compiler and runtime techniques for software transactional memory optimization.
31. The Design of COMPASS: An Execution Driven Simulator for Commercial Applications Running on Shared Memory Multiprocessors.
32. Software Transactional Memory: Why Is It Only a Research Toy?
33. Accuracy and Speedup of Parallel Trace-Driven Architectural Simulation.
34. Relative Performance of Preemption-Safe Locking and Non-Blocking Synchronization on Multiprogrammed Shared Memory Multiprocessors.
35. Coherence Controller Architectures for SMP-Based CC-NUMA Multiprocessors.
36. Transactional memory support in the IBM POWER8 processor.
37. Simple, Fast, and Practical Non-Blocking and Blocking Concurrent Queue Algorithms.
38. The Augmint multiprocessor simulation toolkit for Intel x86 architectures.
39. Implementation of Atomic Primitives on Distributed Shared Memory Multiprocessors.
40. Hazard Pointers: Safe Memory Reclamation for Lock-Free Objects.
41. High-throughout coherence control and hardware messaging in Everest.
42. Coherence Controller Architectures for Scalable Shared-Memory Multiprocessors.
43. Nonblocking Algorithms and Preemption-Safe Locking on Multiprogrammed Shared Memory Multiprocessors.
44. An Efficient Algorithm for Concurrent Priority Queue Heaps.
45. Memory Management in Concurrent Algorithms.
46. A Practical, Scalable, Relaxed Priority Queue
47. Brief announcement: completing the lock-free dynamic cycle.
48. PLDI 2004
49. Software Support and Evaluation of Hardware Transactional Memory on Blue Gene/Q
50. Why the grass may not be greener on the other side
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