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To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.compeleceng.2008.06.002 Byline: Elias Kougianos (a), Saraju P. Mohanty (a), Rabi N. Mahapatra (b) Keywords: Image watermarking; Video watermarking; Digital rights management (DRM); VLSI architectures; Watermarking chip Abstract: Digital media offer several distinct advantages over analog media, such as high quality, ease of editing, and ease of processing operations such as compression and high fidelity copying. Digital data is commonly available through digital TV broadcast, CD, DVD, and computing devices such as personal computers. The ease by which a digital media object can be duplicated and distributed has led to the need for effective digital rights management tools. Digital watermarking is one such tool. Watermarking is the process of embedding extra data called a watermark into a multimedia object, like image, audio, or video, such that the watermark can later be detected or extracted in order to make an assertion regarding the object. During the last decade, numerous software based watermarking schemes have appeared in the literature and watermarking research has attained a certain degree of maturity. But hardware based watermarking systems have evolved more recently only and they are still at their infancy. The goal of hardware assisted watermarking is to achieve low power usage, real-time performance, reliability, and ease of integration with existing consumer electronic devices. In this paper, we survey the hardware assisted solutions proposed in the literature for watermarking of multimedia objects. The survey is preceded by an introduction to the background issues involved in digital watermarking. Author Affiliation: (a) VLSI Design and CAD Laboratory (VDCL), University of North Texas, Denton, TX 76203, United States (b) Department of Computer Science, Texas A&M University, College Station, TX 77843, United States

A new slack distribution scheme is introduced and adopted during the schedule of the task sets in the system and the distribution is made according to the service demand at the nodes which affects the energy consumption in the system. The proposed technique using several benchmarks employing an event driven simulator is evaluated and its performance for multimode applications is demonstrated.

The performance and modeling of the two-dimensional inverse fast cosine transform algorithm on a multiprocessor is investigated. The computational and communication dynamics of the algorithm on multistage interconnection network, shared bus and mesh-connected multiprocessor architectures are analyzed. Results show that the indirect binary n-cube multistage interconnection network architecture outperforms the other architectures in terms of speedup and efficiency.

Support Vector Machine (SVM) is a supervised machine learning model for classification tasks. Training SVM on a large number of data samples is challenging due to the high computational cost and memory requirement. Hence, model training is supported on a high-performance server which typically runs a sequential training algorithm on centralized data. However, as we move towards massive workloads, it will be impossible to store all the data in a centralized manner and expect such sequential training algorithms to scale on traditional processors. Moreover, with the growing demands of real-time machine learning for edge analytics, it is imperative to devise an efficient training framework with relatively cheaper computations and limited memory. Therefore, we propose and implement a first-of-its-kind system of multiple FPGAs as a distributed computing framework comprising up to eight FPGA units on Amazon F1 instances with negligible communication overhead to fully parallelize, accelerate, and scale the SVM training on decentralized data. Each FPGA unit has a pipelined SVM training IP logic core operating at 125 MHz with a power dissipation of 39 Watts for accelerating its allocated computations in the overall training process. We evaluate and compare the performance of the proposed system on five real SVM benchmarks. [ABSTRACT FROM AUTHOR]