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Memristor is a new circuit element defined by a state-dependent Ohm’s law between the memristor voltage and current. It has recently been successfully built, however, its electrical characteristics are not fully known yet. Like other circuit elements R, L and C, there could have various configurations of multiple memristors including serial and parallel connections in a variety of applications. When input voltage/current is supplied to a circuit with multiple memristors, behavior of the device becomes complicated and is difficult to predict. In this chapter, composite characteristics of the serial and parallel connections of memristors are investigated using both linear and nonlinear models. Also, the behavior of individual memristor is formulated mathematically and a general computation method of composite memristance for multiple memristor circuits of diverse configurations is proposed.

In this paper, a generic model of memristive systems, which can emulate the behavior of real memristive devices is proposed. Non-ideal pinched hysteresis loops are sometimes observed in real memristive devices. For example, the hysteresis loops may deviate from the origin over a broad range of amplitude A and frequency f of the input signal. This deviation from the ideal case is often caused by parasitic circuit elements exhibited by real memristive devices. In this paper, we propose a generic memristive circuit model by adding four parasitic circuit elements, namely, a small capacitance, a small inductance, a small DC current source, and a small DC voltage source, to the memristive device. The adequacy of this model is verified experimentally and numerically with two thermistors (NTC and PTC) memristors.

Emulations of memristor-family elements are very important, since their physical realizations are very difficult to achieve with recent technologies. Although some previous studies succeeded in designing memristor and memcapacitor emulators, no significant contribution towards meminductor emulator has been presented so far. The implementation of a meminductor emulator is very important, since real meminductors are not expected to appear in near future. We designed the first meminductor emulator whose inductance can be varied by an external current source without employing any memrisitve system. The principle of our architecture and its feasibility have been verified using SPICE simulation.

This paper presents a simple oscillator using a battery and a second order memristor without the energy storage elements inductor and capacitor. The oscillating mechanism of the proposed circuit has been explained via Hopf bifurcation theorem, small signal model, local activity principle and edge of chaos theorem. This paper can be also used as a reference for explaining the intimate relationship between the super-critical Hopf bifurcation phenomenon and the edge of chaos.

A mutator-based meminductor emulator whose inductance can be varied by an external current source is proposed. The implementation of a meminductor emulator is very important, since real meminductors are not physically realizable with current technology. Though there is active research on memristor or memcapacitor emulators, no significant contribution for the meminductor emulator has been presented yet. In this paper, a meminductor emulator has been built using the principle of a mutator, in that a memristor with $$v-i$$ v - i at one port functions as a meminductor in the other port, whose input is characterized by $$\varphi - i$$ ? - i curve. It is shown that multiple meminductor circuits can be built in various configurations with memristors combined with a single mutator. The feasibility of our meminductor emulator and its expandable configurations are verified experimentally and SPICE simulation.

This exposition shows that the potassium ion-channels and the sodium ion-channels that are distributed over the entire length of the axons of our neurons are in fact locally-active memristors. In particular, they exhibit all of the fingerprints of memristors, including the characteristic pinched hysteresis Lissajous figures in the voltage-current plane, whose loop areas shrink as the frequency of the periodic excitation signal increases. Moreover, the pinched hysteresis loops for the potassium ion-channel memristor, and the sodium ion-channel memristor, from the Hodgkin-Huxley axon circuit model are unique for each periodic excitation signal. An in-depth circuit-theoretic analysis and characterizations of these two classic biological memristors are presented via their small-signal memristive equivalent circuits, their frequency response, and their Nyquist plots. Just as the Hodgkin-Huxley circuit model has stood the test of time, its constituent potassium ion-channel and sodium ion-channel memristors are destined to be classic examples of locally-active memristors in future textbooks on circuit theory and bio-physics.

This paper illustrates that for a device to be a memristor it should exhibit three characteristic fingerprints: 1) When driven by a bipolar periodic signal the device must exhibit a “pinched hysteresis loop” in the voltage-current plane, assuming the response is periodic. 2) Starting from some critical frequency, the hysteresis lobe area should decrease monotonically as the excitation frequency increases, and 3) the pinched hysteresis loop should shrink to a single-valued function when the frequency tends to infinity. Examples of memristors exhibiting these three fingerprints, along with non-memristors exhibiting only a subset of these fingerprints are also presented. In addition, two different types of pinched hysteresis loops; the transversal (self-crossing) and the non-transversal (tangential) loops exhibited by memristors are also discussed with its identification criterion.

Composite characteristics of the parallel and serial connections of memristors are investigated. The memristor is one of the fundamental electrical elements, which has recently been successfully built. However, its electrical characteristics are not yet fully understood. When multiple memristors are connected to each other, the composite behavior of the devices becomes complicated and is difficult to predict, due to the polarity dependent nonlinear variation in the memristance of individual memristors. In this work, we investigate the relationships among flux, charge, and memristance of diverse composite memristors, using both linear and nonlinear memristor models, and analyze the characteristics of complex memristor circuits.

In this paper, we propose a memristor bridge circuit consisting of four identical memristors that is able to perform zero, negative, and positive synaptic weightings. Together with three additional transistors, the memristor bridge weighting circuit is able to perform synaptic operation for neural cells. It is compact as both weighting and weight programming are performed in a memristor bridge synapse. It is power efficient, since the operation is based on pulsed input signals. Its input terminals are utilized commonly for applying both weight programming and weight processing signals via time sharing. In this paper, features of the memristor bridge synapses are investigated using the TiO memristor model via simulations.

A memristor bridge neural circuit which is able to perform signed synaptic weighting was proposed in our previous study, where the synaptic operation was verified via software simulation of the mathematical model of the HP memristor. This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits. In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits. The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

This paper presents a detailed analysis of various oscillatory behaviors observed in relation to the calcium and potassium ions in the third-order Morris–Lecar model of giant barnacle muscle fiber. Since, both the calcium and potassium ions exhibit all of the characteristics of memristor fingerprints, we claim that the time-varying calcium and potassium ions in the third-order Morris–Lecar model are actually time-invariant calcium and potassium memristors in the third-order memristive Morris–Lecar model. We confirmed the existence of a small unstable limit cycle oscillation in both the second-order and the third-order Morris–Lecar model by numerically calculating the basin of attraction of the asymptotically stable equilibrium point associated with two subcritical Hopf bifurcation points. We also describe a comprehensive analysis of the generation of oscillations in third-order memristive Morris–Lecar model via small-signal circuit analysis and a subcritical Hopf bifurcation phenomenon.

In this paper, we present a device to be a memristor should exhibit three characteristic fingerprints: (a) Pinched hysteresis loop in the voltage v vs. current i plane, namely, the v-i loci always passes through origin for any bipolar periodic input voltage v(t). (b) Beyond a certain critical frequency ω*, the area of the pinched hysteresis lobe decreases monotonically as the frequency of the periodic input signal increases and (c) the shape of the pinched hysteresis loop varies with frequency f and shrinks to a single-valued function through the origin, as the frequency tends to infinity. Examples of memristors exhibiting these three fingerprints are presented.

We implemented a memcapacitor emulator with off-the-shelf electronic devices. The memcapacitor is an element whose capacitance can be altered with external current or voltage. The implementation of the emulator is very important since commercial versions are not yet available. The proposed memcapacitor emulator has a simple dedicated memcapacitor architecture that does not require a mutator. It is the first memcapacitor emulator implemented with commercially available devices. The operation as a memcapacitor has been proven via both breadboard experiments and PSPICE simulations.

When multiple memristors are connected to each other, the composite behavior of the devices becomes complicated and is difficult to predict, due to the polarity dependent nonlinear variation in the memristance of individual memristor. In this paper, we investigate the relationships among flux, charge and memristance of diverse composite memristors, using the HP TiO2 model, and analyze the characteristics of complex memristor circuits. It is assumed that all memristor circuits operate at a stable composite memristance state, in which the composite flux curve does not vary and the memristor circuits act as a single memristive system, regardless of input current or voltage. Such study will be conducted for serial and parallel memristor circuits.

The generation of action potentials (oscillations) in biological systems is a complex, yet poorly understood nonlinear dynamical phenomenon involving ions. This paper reveals that the time-varying calcium ion and the time-varying potassium ion, which are essential for generating action potentials in Barnacle giant muscle fibers are in fact generic memristors in the perspective of electrical circuit theory. We will show that these two ions exhibit all the fingerprints of memristors from the equations of the Morris–Lecar model of the Barnacle giant muscle fibers. This paper also gives a textbook reference to understand the difference between memristor and nonlinear resistor via analysis of the potassium ion-channel memristor and calcium ion-channel nonlinear resistor. We will also present a comprehensive in-depth analysis of the generation of action potentials (oscillations) in memristive Morris–Lecar model using small-signal circuit model and the Hopf bifurcation theorem.

A memristor emulator circuit which is designed with off-the-shelf solid state components is presented. As the memristors are not commercially available so far, some circuit replacements which behave like memristors are needed to develop application circuits. In this paper, the variable resistance of a memristor is built utilizing the input resistance of the closed loop circuit of an OP amp. The memristor emulator circuit has been implemented on breadboard with off-the-shelf solid state components. The experimental results of the proposed memristor emulator circuit show a memristor behavior that can be utilized as an alternative of hp TiO2 memristor model.

A simple and compact memristor-based bridge circuit which is able to perform signed synaptic weighting in neuron cells is proposed. The proposed memristor-based synapse is composed of four memristors which makes a bridge type configuration. By programming different values on each memristor of the memristor bridge circuit, weighting values can be set on the memristor bridge synapses. Various simulation results are included.

This paper presents a memristor based new synaptic circuit, consisting of five memristor in a bridge structure together with one differential amplifier. The circuit is able to perform positive and negative weighting for pulse type inputs in neural cells. Processing is conducted with applied pulses at a common terminal in different time slots. It is compact, non-volatile and low power efficient. Simulations of sign setting, weight setting and synaptic multiplication are performed with hp TiO 2 memristor models.

A method to utilize the memristor as a multilevel memory has been proposed. There are several roadblocks in the practical use of memristors for multilevel memory. A difficulty comes from the nonlinearity in the ? vs. q curve which makes it difficult to determine the proper pulse width for desired resistance values. Another one comes from the property of the memristor which integrates any kind of signals including noise that appeared at the memristor and causes memristors to be perturbed from their original values. The proposed method enables the memristor to be used as multilevel memory using a reference resistance array by forcing the memristor to stick at a set of predetermined fixed reference resistance values. We propose the write-in (programming) circuit and the readout/restoration circuit which share the information storing technique using the reference resistance array.

The Cellular Neural Network (CNN) based analog Viterbi decoder with a circular-buffered architecture is proposed for decoding partial response maximum likelihood (PRML) signals. The Viterbi decoder is an error correcting method utilizing the dynamic programming which is an efficient algorithm for finding the optimal path with the identical local computation performed at each node. In the previous CNN-based analog Viterbi decoder, a circularly connected cylindrical structure was presented. In this paper, a multiplexer-based cellular 2D structure is presented in which positions of its decoding and output stages are fixed and a multiplexer which distributes input data sequence to appropriate CNN trellis stages is employed. The proposed CNN-based Viterbi decoder is simpler, requires less silicon area, higher speed and has better performance than the previous one. The principle of the new architecture is uncovered and its decoding performance is compared with that of the previous architecture in this paper.

Contrary to the traditional belief that at least two energy-storage elements (capacitor and/or inductor) and a locally-active nonlinearity are needed to build an electronic oscillator, this paper presents an oscillator made with only two circuit elements, namely, a memristor and a battery. This simplest of all physical oscillators also serves as a textbook example for explaining the intimate relationship between the super-critical Hopf bifurcation phenomenon and the edge of chaos.

In this paper, we propose a memristor emulator that embraces most of features of a real memristor. The important features that a memristor emulator should include are a sufficiently wide range of memristance, bimodal operability of pulse and continuous signal inputs, a long period of nonvolatility, floating operation, operability with other devices, and the ability to be implemented with off-the-shelf devices. The proposed memristor emulator circuit contains all of these features. Specifically, the small variation range of memristance and the nonfloating operation that limit conventional memristor emulators are improved significantly. It is designed to be built with off-the-shelf electronics devices.

Memristor, a new electrical element, can have various configurations of multiple memristors, including serial and parallel connections like previous elements R, L and C. When input voltage/current is supplied to a circuit with multiple memristors, the composite behavior of the memristor circuit exhibits transient states before it enters a steady state. During the transient state period, the behavior is very complex and not predictable due to each memristor's different action depending upon its connection polarity and initial state. In this paper, the transient characteristics of a composite memristor are analyzed via the relationships of charge, flux and memristance of each memristor. Also, the behavior of an individual memristor is formulated mathematically and a general computation method of composite memristance for multiple-memristor circuits of diverse configurations is proposed. Various simulations have also been performed to verify the effectiveness of the proposed method for differently configured memristor circuits, in terms of polarities and initial states.