64 results on '"Mahzoon, Alireza"'
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2. Lower Bound Proof for the Size of BDDs representing a Shifted Addition
3. Introduction
4. SCA-Based Verifier RevSCA-2.0
5. Debugging
6. Reverse Engineering
7. Challenges of SCA-Based Verification
8. Background
9. Local Vanishing Monomials Removal
10. Dynamic Backward Rewriting
11. Conclusion and Outlook
12. Polynomial Formal Verification of Complex Circuits Using a Hybrid Proof Engine
13. Start Small But Dream Big: On Choosing a Static Variable Order for Multiplier BDDs
14. Formal Verification of Structurally Complex Multipliers
15. Conclusion and Outlook
16. Debugging
17. Introduction
18. Challenges of SCA-Based Verification
19. SCA-Based Verifier RevSCA-2.0
20. Polynomial Formal Verification of Arithmetic Circuits
21. GenMul: Generating Architecturally Complex Multipliers to Challenge Formal Verification Tools
22. Polynomial Formal Verification of Arithmetic Circuits
23. Polynomial Formal Verification of a Processor: A RISC-V Case Study
24. Lower Bound Proof for the Size of Bdds Representing a Shifted Addition
25. Investigating Various Adder Architectures for Digital In-Memory Computing Using MAGIC-based Memristor Design Style
26. Lower Bound Proof for the Size of Bdds Representing a Shifted Addition
27. Monitoring the Effects of Static Variable Orders on the Construction of BDDs
28. Polynomial Formal Verification
29. ANN-based Performance Estimation of Embedded Software for RISC-V Processors
30. Preserving Design Hierarchy Information for Polynomial Formal Verification
31. Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability
32. Polynomial Formal Verification of General Tree-Like Circuits
33. RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal
34. Towards Polynomial Formal Verification of Complex Arithmetic Circuits
35. Design Modification for Polynomial Formal Verification
36. Late Breaking Results: Polynomial Formal Verification of Fast Adders
37. Polynomial word-level verification of arithmetic circuits
38. Polynomial Formal Verification of Prefix Adders
39. Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization
40. ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Technique
41. Towards Formal Verification of Optimized and Industrial Multipliers
42. The Thereminic Room Interface : Interfacing a Room sized Instrument for Multiple Players
43. RevSCA
44. PolyCleaner
45. Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers
46. RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers.
47. Systematic Design Space Exploration of Floating-Point Expressions on FPGA
48. OptiFEX: A Framework for Exploring Area-Efficient Floating Point Expressions on FPGAs With Optimized Exponent/Mantissa Widths
49. The Effect of Visualisation on a Cognitively Demanding Task
50. Manipulated Private and Public Spheres : The Use of Control Technologies by Totalitarian Regimes
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