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This article proposes a method of generating 24-sided polygonal voltage space vector structure composed of 24 real active vectors and a zero vector. Each active vector is a real vector in contrast to switched average vectors in literature. Generation of real 24-sided vectors minimizes switching losses and improves quality of phase voltage compared to switched averaged vectors technique. An important feature of the presented scheme is elimination of lower order harmonics up to 19th order from motor phase voltage throughout the modulation range that gives reduction in torque pulsation and near sinusoidal phase current. The proposed scheme extends the linear modulation range till 99.42 $\%$. Open-end winding induction motor is fed with primary and secondary inverters from either ends. Primary and secondary inverters are implemented by cascading two-level inverters. DC sources for both the inverters are realized using a simple star-delta transformer combination. The proposed concepts are verified with laboratory prototype and the respective results during the steady-state, transient, and fault scenario are presented. The supporting loss analysis and harmonic performance of the proposed drive is performed with existing topologies. [ABSTRACT FROM AUTHOR]

With the integration of renewable energy sources into the power grid, a number of power electronic converters need to be connected together in parallel. Due to this interconnection among the power converters with a common DC bus, the equivalent impedance of the DC network, i.e., DC network impedance (DCNI) of these parallel converters, may vary and can cause oscillations in the DC link voltage (DCLV). In the literature, impedance models of grid-tied converters (GCs) based on the AC side are well reported without including these variations in DCNI. In addition, the dynamics of a phase-locked loop (PLL) play a significant role in GC system stability. To evaluate these stability issues, this paper proposes small signal impedance models viewing from the DC side of a three-phase GC operating under different control modes considering the PLL dynamics and the DCNI variations. Using the proposed DC impedance models (DCIM), DCLV stability analysis is evaluated for a GC. It is verified through bode plots that the interaction between the proposed DCIM and DCNI leads to unstable operation of the closed-loop converter near the PLL bandwidth when the phase difference between DCIM and DCNI is more than 180 degrees. Finally, the analytically developed models are validated using hardware in-the-loop (HIL) testing. [ABSTRACT FROM AUTHOR]

A voltage source inverter generating a polygonal voltage space vector structure (SVS) having 117- concentric 30-sided polygons of different radii are proposed. Modulation using a 30-sided SVS eliminates lower order harmonics till 25th order from motor phase voltage. The proposed scheme combines the advantages of a 30-sided SVS with that of a multilevel inverter. The topology consists of two cascaded five-level inverters feeding from either end of the open-end induction motor stator windings. One of the cascaded five-level inverter is connected to an active dc source and delivers the required active power for the scheme, while the other is capacitor fed and acts as a switched capacitive filter. In this article, nonaligned 30-sided polygons, i.e., regular 30-sided polygons that are not symmetric with respect to $\alpha$ and $\beta$ axis are also considered for inverter operation. The harmonic analysis of such nonaligned 30-sided polygons is investigated in this article. Nearest level switching is employed throughout the modulation range, enabling further reduction of switching loss in the system. Extensive hardware experimentations are carried out to validate the proposed scheme and the results are included in the article. [ABSTRACT FROM AUTHOR]

Modulation using a higher sided polygonal space vector structure (SVS) is an elegant method to increase the linear modulation range and to eliminate the undesired lower order harmonics from motor phase voltage. This article presents the generation of a dense 15-concentric 30-sided multilevel SVS using a single dc-link for an open end induction motor (OEIM) drive. The proposed scheme eliminates lower order harmonics till 25th order from motor phase voltage throughout the modulation range. The $dv/dt$ stress in the phase voltage applied to the motor will also be highly reduced owing to the multilevel structure. The pulsewidth modulation scheme employed utilizes the denseness of SVS and avoids iterative searches to find the triangle, which encompasses the tip of reference voltage vector, which are typical in multilevel polygonal SVS. The topology consists of an active dc-link fed three-level primary inverter and a capacitor fed five-level secondary inverter connected to either end of an OEIM. The primary inverter acts as the active power supplier for the drive and the secondary inverter filters out the undesirable lower order harmonics from motor phase voltage. The proposed scheme is experientially validated and the results are included in this article. [ABSTRACT FROM AUTHOR]

In this article, a multilevel inverter scheme to generate a 30-sided space vector structure (SVS) with congruent triangles is proposed. The 30-sided SVS eliminates all the lower order harmonics till 25th order from motor phase voltage throughout the modulation range. The proposed scheme is implemented using a single dc-link on an open-end induction motor (OEIM). The OEIM is fed with primary inverter from one end and secondary inverter from the other end. Primary inverter is fed from an active dc-link and supplies all the required active power for the scheme. Secondary inverter is a capacitor fed inverter, which acts as the switched capacitive filter. In this work, a simple algorithm is proposed, which calculates the timings required for a 2-level 30-sided SVS from sampled reference voltages. The algorithm requires only simple operations such as addition, multiplication, and comparisons. From the obtained timing values, the space vector location of three nearest multilevel 30-sided vectors and its time duration can be identified. The feasibility of the proposed scheme is proved by experimental results. [ABSTRACT FROM AUTHOR]

This article introduces a hybrid nine-level inverter topology with extended dc-bus utilization for operation at over modulation range without the presence of lower order harmonics (predominantly fifth and seventh) when compared to conventional two-level and multilevel inverter with hexagonal voltage space vector structure. The proposed inverter is a cascade of a five-level T-type unit and an H-bridge (HB) unit. An increase in the dc-bus utilization is possible by increasing the pole voltage levels to ± (Vdc/2 + Vdc/8) using the HB capacitor voltage and also the capacitor voltages are balanced by adding a offset to sine reference. The aforementioned pulsewidth modulation strategy allows us to increase the peak phase fundamental voltage from 0.577Vdc to 0.625Vdc in case of unity power factor (p.f) load and to 0.637Vdc for 0.82 p.f load with the proposed nine-level inverter. The limiting factor on increasing the dc bus utilization such as p.f, HB capacitor balancing are analysed broadly in this article. The proposed inverter scheme and its claim of increasing the peak phase fundamental voltage is experimentally validated in a laboratory prototype. [ABSTRACT FROM AUTHOR]

In this article, a method is proposed for the first time, to increase the linear modulation range till full base speed irrespective of load power factor for a multilevel inverter fed induction motor drive. A five-level inverter with a single dc source is used for the proposed scheme. Using this method, linear pulsewidth modulation (PWM) operation of the inverter can be achieved till peak phase fundamental voltage of 0.637 Vdc without exceeding machine phase voltage rating. This method eliminates all the lower order harmonics from machine phase voltage till the full speed range of operation. The proposed five-level inverter scheme is realized by cascading a two-level inverter with a capacitor fed H-bridge, feeding open-end induction motor drive from one end and a capacitor fed two-level inverter from the other end. The proposed scheme uses space vector redundancy to balance all the capacitors during its operation. Operation of the proposed drive is analyzed extensively for normal five-level operation as well as during the extended modulation range. Experimental results for steady state and transient state operation are presented to validate the proposed scheme [ABSTRACT FROM AUTHOR]

This paper presents a 5-level inverter topology for open-end induction motor drives by using a single dc source. The open stator windings of the drive are supplied with a 3-level flying capacitor inverter from one end and capacitor-fed 2-level inverter from another end. The voltage ratio of the dc link to the capacitor in 2-level inverter is maintained at 4:1 ratio to generate five-level voltage output. The capacitor in 2-level inverter is balanced by the switching redundant vector combinations from both the inverters while the floating capacitors in the 3-level inverter are balanced by using redundant switching states. The proposed topology gives 5-level operation with less number of floating capacitors and power semiconductor switches compared to other existing topologies. Also, the balancing of the capacitors is independent of load power factor and modulation index. Further, the generalization of the proposed dual inverter scheme for any n-level inverter is also included in this paper. The experimental results and required analysis are also presented to validate the inverter scheme. [ABSTRACT FROM AUTHOR]

In this article, a nine-level multilevel topology is proposed by stacking of low voltage basic inverter cells and then cascading with H-bridges. The dc-link is split into four equal halves by series-connected capacitors from a common dc-link. Three common coupling points (CCPs) are formed due to the stacking of four capacitors, which are connected across the dc-link. The CCP voltage balancing is ensured by drawing or injecting zero instantaneous currents from each of these points at any instant. A six-phase symmetrical IM is used to generate equal and opposite instantaneous phase currents by applying exactly equal and opposite phase voltages for two opposite phases from the six-phase inverter. Simultaneously, the capacitor voltage balancing of H-bridge inverter cells is also achieved by proper selection of redundancies from the available pole voltage redundancies. The concept is verified with a nine-level inverter laboratory prototype, which consists of a five-level stacked inverter, and followed by two low voltage cascaded H-bridge inverters in each phase. Detailed experimental results of steady-state and transient conditions are included to validate the proposed scheme. [ABSTRACT FROM AUTHOR]