146 results on '"Mak, Wai-Kei"'
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2. Optimization for Buffer and Splitter Insertion in AQFP Circuits with Local and Group Movement
3. Efficient Qubit Routing Using a Dynamically-Extract-and-Route Framework
4. Hybrid-Row-Height Design Placement Legalization Considering Cell Variants
5. A routing framework for technology migration with bump encroachment
6. Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization
7. Reinforcement Learning and DEAR Framework for Solving the Qubit Mapping Problem
8. Linear-time Mixed-Cell-Height Legalization for Minimizing Maximum Displacement
9. HybridGP: Global Placement for Hybrid-Row-Height Designs*
10. Drain-to-Drain Abutment-Aware Detailed Placement Refinement for Power Staple Insertion Optimization
11. A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum Logic Circuits with Maximum Path Length Consideration
12. A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum (SFQ) Logic Circuits
13. Drain-to-Drain Abutment-Aware Detailed Placement Refinement for Power Staple Insertion Optimization
14. Multiple-Layer Multiple-Patterning Aware Placement Refinement for Mixed-Cell-Height Designs
15. Pin Assignment Optimization for Multi-2.5D FPGA-Based Systems With Time-Multiplexed I/Os
16. Manufacturing-Aware Power Staple Insertion Optimization by Enhanced Multi-Row Detailed Placement Refinement
17. I/O placement for FPGAs withmultiple I/O standards
18. Temporal logic replication for dynamically reconfigurable FPGA partitioning
19. Min-cut partitioning with functional replication for technology-mapped circuits using minimum area overhead
20. Minimum replication min-cut partitioning
21. On optimal board-level routing for FPGA-based logic emulation
22. A practical detailed placement algorithm under multi-cell spacing constraints
23. Guest Editorial: Field Programmable Technology
24. A fast hypergraph min-cut algorithm for circuit partitioning
25. Pin Assignment Optimization for Multi-2.5D FPGA-based Systems
26. Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration
27. Making split fabrication synergistically secure and manufacturable
28. Monte Carlo bounding techniques for determining solution quality in stochastic programs
29. Self-Aligned Double Patterning Lithography Aware Detailed Routing With Color Preassignment
30. Minimum Implant Area-Aware Placement and Threshold Voltage Refinement
31. Mixed-Cell-Height Standard Cell Placement Legalization
32. Pin Accessibility-Driven Detailed Placement Refinement
33. Optimizing DSA-MP decomposition and redundant via insertion with dummy vias
34. Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability consideration
35. Optimizing Pin Assignment and Escape Routing for Blind-via-Based PCBs
36. Minimum implant area-aware placement and threshold voltage refinement
37. Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations
38. Flexible Packed Stencil Design With Multiple Shaping Apertures and Overlapping Shots for E-beam Lithography
39. An institutional perspective of the China-based companies in Hong Kong
40. Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography
41. Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout
42. Double patterning-aware detailed routing with mask usage balancing
43. A novel wirelength-driven packing algorithm for FPGAs with adaptive logic modules
44. Flexible packed stencil design with multiple shaping apertures for e-beam lithography
45. Simultaneous Constrained Pin Assignment and Escape Routing Considering Differential Pairs for FPGA-PCB Co-Design
46. MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules
47. Detailed routing for Spacer-Is-Metal type Self-Aligned Double/Quadruple Patterning Lithography.
48. Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement
49. Rethinking the Wirelength Benefit of 3-D Integration
50. Power-Driven Flip-Flop Merging and Relocation
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