234 results on '"Manuel E. Acacio"'
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2. Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing.
3. CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions.
4. Speculative inter-thread store-to-load forwarding in SMT architectures.
5. STIFT: A Spatio-Temporal Integrated Folding Tree for Efficient Reductions in Flexible DNN Accelerators.
6. Understanding the Design-Space of Sparse/Dense Multiphase GNN dataflows on Spatial Accelerators.
7. Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory.
8. On the interactions between ILP and TLP with hardware transactional memory.
9. Analysing software prefetching opportunities in hardware transactional memory.
10. DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory.
11. A novel network fabric for efficient spatio-temporal reduction in flexible DNN accelerators.
12. ITSLF: Inter-Thread Store-to-Load Forwardingin Simultaneous Multithreading.
13. STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators.
14. CNN-SIM: A Detailed Arquitectural Simulator of CNN Accelerators.
15. PfTouch: Concurrent page-fault handling for Intel restricted transactional memory.
16. Ant Colony Optimization-Based Streaming Feature Selection: An Application to the Medical Image Diagnosis.
17. A Machine Learning Gateway for Scientific Workflow Design.
18. Concurrent Irrevocability in Best-Effort Hardware Transactional Memory.
19. SAWS: Simple and Adaptive Warp Scheduling for Improved Performance in Throughput Processors.
20. A Taxonomy for Classification and Comparison of Dataflows for GNN Accelerators.
21. Way Combination for an Adaptive and Scalable Coherence Directory.
22. InsideNet: A tool for characterizing convolutional neural networks.
23. Way-combining directory: an adaptive and scalable low-cost coherence directory.
24. Photonic-based express coherence notifications for many-core CMPs.
25. Parallel implementations of the 3D fast wavelet transform on a Raspberry Pi 2 cluster.
26. On the Parallelization of Stream Compaction on a Low-Cost SDC Cluster.
27. STONNE: A Detailed Architectural Simulator for Flexible Neural Network Accelerators.
28. Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence.
29. To be silent or not: on the impact of evictions of clean data in cache-coherent multicores.
30. Early Experiences with Separate Caches for Private and Shared Data.
31. Foreword to the Special Issue on Processors, Interconnects, Storage, and Caches for Exascale Systems.
32. Are distributed sharing codes a solution to the scalability problem of coherence directories in manycores? An evaluation study.
33. Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs.
34. ECONO: Express coherence notifications for efficient cache coherency in many-core CMPs.
35. Towards Efficient Dynamic LLC Home Bank Mapping with NoC-Level Support.
36. Deploying Hardware Locks to Improve Performance and Energy Efficiency of Hardware Transactional Memory.
37. Efficient Dir0B Cache Coherency for Many-Core CMPs.
38. An Experience of Early Initiation to Parallelism in the Computing Engineering Degree at the University of Murcia, Spain.
39. Heterogeneous NoC Design for Efficient Broadcast-based Coherence Protocol Support.
40. Dynamic Last-Level Cache Allocation to Reduce Area and Power Overhead in Directory Coherence Protocols.
41. Dynamic Serialization: Improving Energy Consumption in Eager-Eager Hardware Transactional Memory Systems.
42. Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs.
43. ASCIB: adaptive selection of cache indexing bits for removing conflict misses.
44. π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory.
45. Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs.
46. The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems.
47. GLocks: Efficient Support for Highly-Contended Locks in Many-Core CMPs.
48. Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory.
49. ZEBRA: a data-centric, hybrid-policy hardware transactional memory design.
50. Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs.
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