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Template-assisted selective area growth techniques have gained popularity for their ability to grow epitaxial materials in prefabricated dielectric templates. Confined epitaxial lateral overgrowth (CELO) is one such technique that uses dielectric templates to define the geometry of the grown nanostructures. Two terminal low-temperature magneto-transport measurements were used to determine electronic properties. For doped In0.53Ga0.47As CELO nanostructures, we observe Shubnikov–De Hass oscillations in the longitudinal magnetoresistance and utilize these to estimate effective mass, carrier density, and mobilities. This analysis both reveals the presence of defects in these nanostructures and material variabilities between growth runs. Electron beam lithography and contact deposition for transport measurements were enabled by parasitic growth removal. In the future, this approach can enable other material systems to be explored for confined lateral epitaxy, improve material quality, and investigate a variety of quantum transport phenomenon in such nanoscale devices. [ABSTRACT FROM AUTHOR]

Selectively growing epitaxial material in confined dielectric structures has been explored recently as a pathway to integrate highly mismatched materials on silicon substrates. This approach involves the fabrication of a channel-like structure of dielectric material that from the growth atmosphere reaches down to a small exposed area of the substrate where subsequent growth via metal organic chemical vapor deposition (MOCVD) initiates. The technique, referred to as template assisted selective epitaxy, can also enable the development of novel nanoscale photonic and electronic device structures because of its ability to allow epitaxy to progress in a direction, final size, and aspect ratio defined by the dielectric template, and allows integration of horizontal heterojunction inside the channel. To date, most confined epitaxy work has been detailed on silicon. Due to the reduced chemical and thermal stability of InP compared to Si, additional steps for surface preparation are required. In this work, two different fabrication routes are described on InP substrates: one involving amorphous silicon as a sacrificial layer and deposited SiO2 as top oxide, while the other involves spin coated photoresist and hydrogen-silsesquioxane sourced SiOx. Both routes, leading to similar template structures, are demonstrated and discussed. Homoepitaxy of InP in both types of templates and the integration of an InAs horizontal heterojunction are demonstrated via MOCVD. An increase in growth rate with decreasing template length, increasing template width, and decreasing pattern density is observed. [ABSTRACT FROM AUTHOR]

We report Lg= 30 nm InAs-channel MOSFETs exhibiting 420 GHz f\textit {max} , record for a III-V MOSFET, and 357 GHz ft . The device incorporates a 5-nm strained InAs channel grown on an InP substrate. To reduce the parasitic gate-source and gate-drain capacitances, regrown lateral access regions increase the separations between the gate and the N+ source and drain; modulation doping within these access regions provides a low associated series resistance, enabling high gm . The 30 nm Lg device shows an 1.5 mS/ \mu \textm DC peak extrinsic gm at V\textit {DS} = 0.5 V and V\textit {GS} = 0.3 V, 91% of the value (1.65 mS/ \mu \textm ) extracted from 10 MHz RF measurements, indicating a low DC-RF dispersion. [ABSTRACT FROM AUTHOR]