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Developing an academic programme that upskills students and enhances employability can be a challenge, however getting that ‘spark’ of an idea can come from unexpected places. Programme design can be improved through collaboration with different subject areas and with employers. Audio and Video forensics is a fast-moving area at the forefront of evidence in the criminal justice system. The need for improving knowledge, skills and abilities of audio & video forensic officers has been acknowledged by the Ministry of Justice, the UK Forensic Regulator and the National Police Chiefs Council, with plans for all audio & video forensic officers to be educated and trained to the highest level. Having taught Audio Production for many years, the Audio Team introduced a popular and well received Audio Forensics module. Based on this, and through a working relationship with the Forensic Science team (School of PBS), the School of Engineering started discussions with Merseyside Police in relation to audio and video forensics. This collaboration led to creating the MSc in Audio and Video Forensics (validated in July 2021) delivered primarily online. Given this MSc in Audio and Video Forensics is the only such programme in the world, LJMU are ideally placed to be at the forefront of this educational upskilling. Senior Officers within Merseyside Police generally and the Merseyside Police Forensic Unit in particular, have been closely involved in developing the MSc programme, with their support extending to sending a significant number of their staff to study on the programme. The talk will detail the collaboration between LJMU departments, students, and Police during the design process to produce a programme that meets the needs of Police Forensic Units, provides a route for Audio/Video Technology graduate to retrain into forensics, and provides graduates with the requisite transversal skills – an approach that other departments can follow., Student Experience Proceedings, 2022: Students at the Heart Conference

In 2011 the International Technology Roadmap for Semiconductors, ITRS 2011, outlined how the semiconductor industry should proceed to pursue Moore’s Law past the 18nm generation. It envisioned a concept of ‘More than Moore’, in which existing semiconductor technologies can be exploited to enable the fabrication of diverse systems and in particular systems which integrate non-digital and biologically based functionality. A rapid expansion and growing interest in the fields of microbiology, electrophysiology, and computational neuroscience occurred. This activity has provided significant understanding and insight into the function and structure of the human brain leading to the creation of systems which mimic the operation of the biological nervous system. As the systems expand a need for small area, low power devices which replicate the important biological features of neural networks has been established to implement large scale networks. In this thesis work is presented which focuses on the modification and storage of synaptic weights in hardware neural networks. Test devices were incorporated on 3 chip runs; each chip was fabricated in a 0.35μm process from Austria MicroSystems (AMS) and used for parameter extraction, in accordance with the theoretical analysis presented. A compact circuit is presented which can implement STDP, and has advantages over current implementations in that the critical timing window for synaptic modification is implemented within the circuit. The duration of the critical timing window is set by the subthreshold current controlled by the voltage, Vleak, applied to transistor Mleak in the circuit. A physical model to predict the time window for plasticity to occur is formulated and the effects of process variations on the window is analysed. The STDP circuit is implemented using two dedicated circuit blocks, one for potentiation and one for depression where each block consists of 4 transistors and a polysilicon capacitor, and an area of 980µm2. SpectreS simulations of the back-annotated layout of the circuit and experimental results indicate that STDP with biologically plausible critical timing windows over the range 10µs to 100ms can be implemented. Theoretical analysis using parameters extracted from MOS test devices is used to describe the operation of each device and circuit presented. Simulation results and results obtained from fabricated devices confirm the validity of these designs and approaches. Both the WP and WD circuits have a power consumption of approximately 2.4mW, during a weight update. If no weight update occurs the resting currents within the device are in the nA range, thus each circuit has a power consumption of approximately 1µW. A floating gate, FG, device fabricated using a standard CMOS process is presented. This device is to be integrated with both the WP and WD STDP circuits. The FG device is designed to store negative charge on a FG to represent the synaptic weight of the associated synapse. Charge is added or removed from the FG via Fowler-Nordheim tunnelling. This thesis outlines the design criteria and theoretical operation of this device. A model of the charge storage characteristics is presented and verified using HFCV and PCV experimental results. Limited precision weights, LPW, and its potential use in hardware neural networks is also considered. LPW offers a potential solution in the quest to design a compact FG device for use with CTS. The algorithms presented in this thesis show that LPW allows for a reduction in the synaptic weight storage device while permitting the network to function as intended.