155 results on '"Martinie, S."'
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2. Material level analytical model of total ionizing dose induced DC characteristics shift for FDSOI IC design
3. Non-Quasi-Static modeling and methodology in fully depleted SOI MOSFET for L-UTSOI model
4. Poisson-Schrödinger simulation and analytical modeling of inversion charge in FDSOI MOSFET down to 0 K – Towards compact modeling for cryo CMOS application
5. On the modelling of temperature dependence of subthreshold swing in MOSFETs down to cryogenic temperature
6. A2RAM compact modeling: From DC to 1T-DRAM memory operation
7. Impact of roughness of TiN bottom electrode on the forming voltage of HfO2 based resistive memories
8. New prospects on high on-current and steep subthreshold slope for innovative Tunnel FET architectures
9. Doping profile extraction in thin SOI films: Application to A2RAM
10. New insights on SOI Tunnel FETs with low-temperature process flow for CoolCube™ integration
11. A review of the Z2-FET 1T-DRAM memory: Operation mechanisms and key parameters
12. TCAD simulation methodology of total ionizing dose effects for PDSOI transistor with a hump characteristic
13. Ultra-low power 1T-DRAM in FDSOI technology
14. Reconfigurable field effect transistor for advanced CMOS: Advantages and limitations
15. Fabrication and electrical characterizations of SGOI tunnel FETs with gate length down to 50 nm
16. Investigation of ambipolar signature in SiGeOI homojunction tunnel FETs
17. Fabrication of Low-Power RRAM for Stateful Hyperdimensional Computing
18. A Simple Compact Model to Analyze the Impact of Ballistic and Quasi-Ballistic Transport on Ring Oscillator Performance
19. Improved measurement of electric fields by nanobeam precession electron diffraction.
20. Behavioral modeling of SRIM tables for numerical simulation
21. FDSOI for cryoCMOS electronics: device characterization towards compact model
22. Soft-errors induced by terrestrial neutrons and natural alpha-particle emitters in advanced memory circuits at ground level
23. Comprehensive TCAD Analysis of Threshold Voltage on GaN-on-Si MOS-Channel Fully Recessed Gate HEMTs
24. Physics-based analytical modeling of quasi-ballistic transport in double-gate MOSFETs: from device to circuit operation
25. In depth TCAD analysis of threshold voltage on GaN-on-Si MOS-channel fully recessed gate HEMTs
26. Poisson-Schrödinger simulation of inversion charge in FDSOI MOSFET down to 0K - Towards compact modeling for cryo CMOS application
27. SEU Prediction for Very Integrated Circuits based on Advanced Physical Considerations
28. Total Ionizing Dose Effects in FDSOI Compact Model for IC Design
29. Pure boron monolayer to boost A2RAM performance
30. Modeling of the bridge threshold voltage in A2RAM cell
31. Z²-FET DC hysteresis: deep understanding and preliminary model
32. Tunability of Parasitic Channel in Gate-All-Around Stacked Nanosheets
33. A review of the Z 2 -FET 1T-DRAM memory: Operation mechanisms and key parameters
34. Kubo-Greenwood approach for the calculation of mobility in gate-all-around nanowire metal-oxide-semiconductor field-effect transistors including screened remote Coulomb scattering-Comparison with experiment.
35. Doping profile extraction in thin SOI films: Application to A2RAM
36. Performance and design considerations for gate-all-around stacked-NanoWires FETs
37. Z2-FET SPICE model: DC and memory operation
38. Optimization guidelines of A2RAM cell performance through TCAD simulations
39. The mystery of the Z2-FET 1T-DRAM memory
40. First SOI Tunnel FETs with low-temperature process
41. Stacked-Nanowires and FinFET Transistors: Guidelines fo the 7nm Technology
42. 2D TCAD strain simulations from fully depleted to nanowire transistors: efficiency of mechanical stressors
43. Study of the piezoresistive properties of NMOS and PMOS Ω-gate SOI nanowire transistors: Scalability effects and high stress level
44. NSP: Physical compact model for stacked-planar and vertical Gate-All-Around MOSFETs
45. Reconfigurable FET SPICE model for design evaluation
46. First Demonstration of Strained SiGe Nanowires TFETs with ION beyond 700μA/μm
47. Simulation TCAD du transis-tor Tri-Gate sur SOI
48. Challenges of modeling the Split-Gate SuperFlash® Memory Cell with 1.1V Select Transistor
49. Parasitic Capacitance Analytical Model for Sub-7-nm Multigate Devices
50. Reconfigurable field effect transistor for advanced CMOS: A comparison with FDSOI devices
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