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Low temperature (≤400 °C) formation of orientation-controlled large (≥10 µm) Ge-on-insulator (GOI) structures is desired to fabricate 3-dimensional large-scale integrated circuits (LSIs), where Ge-based functional devices are stacked on Si-LSIs. For this purpose, Si-seeded pulse-laser annealing (PLA) combined with low-temperature substrate heating (≤400 °C) has been developed. Here, a-Ge stripes on Si substrates partially covered with insulating films are subjected to PLA, where single edges of the a-Ge stripes directly contact Si-seeding substrates through opening windows of insulating films. PLA at room temperature generates lateral growth of Ge layers from Si-seeding substrates. However, the growth length is short (~1 µm), which is attributed to very short melting time. To increase the melting time, low-temperature (≤400 °C) substrate heating during PLA is examined. As a result, very large (~20 µm) orientation-controlled GOI is obtained by combining substrate heating (400 °C) with PLA. Detailed electron microscopy analysis reveals very high crystallinity of the grown layers. Consequently, high-quality rapid-melting growth of Ge becomes possible at a low processing temperature of ~400 °C. This thermally-assisted (~400 °C) Si-seeded PLA will facilitate realization of 3-dimensional LSIs.

Low-temperature formation of Sn-doped Ge on insulator is desired to realize next generation flexible electronics. To achieve this, metal-induced crystallization (MIC) of a-GeSn is investigated. By MIC of a-GeSn with initial Sn concentration of 5%, Sn-doped Ge is obtained at low temperatures ( Introduction A technique for low-temperature (≤250°C) formation of high-quality crystalline Ge films on insulator is expected to realize advanced high performance thin film transistors (TFT) on flexible plastic substrates (softening temperature: ~300oC). To improve quality of Ge crystals, Sn-doping (2layers [2]. However, the growth temperature (425°C) reported to date is higher than the softening temperatures of plastic substrates. To decrease the growth temperature of Sn-doped Ge, in the present study, we investigate metal-induced crystallization (MIC) of a-GeSn. This successfully decreases the growth temperature below 250°C. Experimental Procedure Fig.1 schematically shows the procedure of sample preparation. Amorphous Ge1-xSnx layers (x: 0-0.2, thickness: 100 nm) were deposited on quartz substrates at room temperature. Then, Au layer patterns were formed on the amorphous GeSn layers. The samples were annealed at 150-250oC for 10-60 min to induce lateral growth in a N2ambient. The growth characteristics were analyzed by Nomarski optical microscopy and microprobe Raman spectroscopy. Results and Discussion Figs. 2(a) and 2(b) show Nomarski optical micrographs of Ge1-xSnx (x: 0.05 and 0.2, respectively) samples after annealing at 250oC for 10 min. Au pattern regions are located in the left side areas of the micrographs. In the case of the low Sn concentration (5%), different contrast regions are observed around the Au patterns, as indicated by the broken lines. On the other hand, the sample with the high Sn concentration (20%) shows no change around the Au pattern after annealing. The Raman spectra obtained from these samples are summarized in Fig. 2(c). In Raman spectra #1 for the low Sn concentration (5%), a sharp peak due to Ge-Ge bonding in c-Ge is clearly observed. On the other hand, no peaks are detected in spectra #3 for the sample with the high Sn concentration (20%). These results indicate that lateral growth is generated from the Au patterns for samples with the low Sn concentration (5%), while it is not generated for the high Sn concentration (20%).The lateral growth lengths at 150 and 250oC for samples with various Sn concentrations were estimated using theNomarski optical microscopy combined with line-scanning of microprobe Raman measurements. The results are summarized as a function of the annealing time in Fig. 3. In the case of low Sn concentrations ( References [1] O. Nakatsuka, et al., Jpn. J. Appl. Phys. Lett. 49, 04DA10 (2010). [2] W. Takeuchi, et al., Appl. Phys. Lett. 107, 022103 (2015). Figure 1

Structural and electrical properties of a Ge(111) layer directly grown on a Si(111) substrate are studied. Via optimized two-step growth manner, we form a high-quality relaxed Ge layer, where strain-relieving dislocations are confined close to a Ge/Si interface. Consequently, a density of holes, which unintentionally come from crystal defects, is highly suppressed below 4 × 10 16 cm − 3 , which leads to significantly high hole Hall mobility exceeding 1500 cm 2 /Vs at room temperature. By layer transfer of the grown Ge layer, we also fabricate a Ge(111)-on-Insulator, which is a promising template for high-performance Ge-based electronic and photonic devices.

GeSn with a high substitutional Sn concentration (> 7%) is an attractive direct band gap material for high-efficiency photodevices that can be merged with large-scale integrated circuits (LSIs). To achieve GeSn with high Sn concentration, low-temperature solid-phase epitaxy using amorphous-GeSn (a-GeSn) (Sn concentration: 10%–36%)/crystal-Ge (c-Ge) stacked structures was investigated. Solid-phase growth of GeSn was enhanced as Sn concentration was increased, which enabled epitaxial growth at very low temperature (150–200 °C). Interestingly, concentrations of substitutional Sn increased with decreasing growth temperature. As a result, epitaxial growth of GeSn with substitutional Sn concentrations of ~ 8% was achieved by decreasing the growth temperature to 150 °C using a-GeSn (Sn concentration: 36%)/c-Ge stacked structures. This technique is expected to be useful to realize multi-function LSIs, where high-efficiency photodevices are integrated with transistors.

I NTRODUCTION Low-temperature (≤300oC) formation of quasi-single crystal SiGe, i.e., orientation-controlled large-grain crystal (≥10 μm) SiGe, on insulator is desired for realization of advanced flexible electronics, where high-speed transistors and high-efficiency optical devices are integrated on flexible plastics substrates (softening temperature: ~350°C). This is because SiGe provides higher carrier mobility and superior optical properties compared with Si. Recently, we developed gold-induced layer-exchange crystallization (GIC) using a-Ge/Au stacked structures.[1-3] This enabled selective formation of (100)- or (111)-oriented large-grain Ge (≥20 μm) through controlling nucleation during GIC by using anisotropic surface energy on substrates.[1] We have developed this technique onto plastic and realized orientation-controlled large-grain crystals on flexible plastic substrates with low concentration holes (~2×1017 cm-3), which enables high carrier mobility (~160 cm2/Vs).[2,3] However, reports of orientation-controlled growth by GIC are limited to pure Ge crystals so far. In the present study the GIC technique is developed to SiGe. Consequently, quasi-single crystal SiGe is achieved on insulating substrates at low temperatures (~300oC). EXPERIMENTAL The sample structure and experimental procedure are schematically shown in Fig. 1. In the experiment, fused-quartz chips were employed as substrates. On the substrates, a-SiGe (Ge concentration: 0-100%, thickness: 100 nm) /Au (thickness: 100 nm) stacked structures were formed. Here, amorphous Al2O3 interface-layers (thickness: 4-7 nm) were introduced between a-SiGe and Au layers as diffusion barrier to make interface-nucleation dominate over random bulk-nucleation in Au layers.[1] These samples were annealed at 250-300oC to induce crystallization. The grown layers were analyzed by Nomarski optical microscopy, electron backscattering diffraction (EBSD), and micro-probe Raman scattering spectroscopy (excitation-laser spot-diameter: ~1 μm). The Nomarski optical microscopy observations were carried out from the back sides of the samples through the transparent quartz substrates to characterize the bottom layers. RESULTS AND DISCUSSION The growth features of samples with various Ge fractions and Al2O3 interface layer thicknesses were investigated by Nomarski optical microscopy observations after annealing at 250°C for 50 h. Typical Nomarski micrographs of samples with Ge concentrations of 50% and 100% are shown in Figs. 2(a)-2(b) and 2(c)-2(d), respectively. In these micrographs, dark and bright contrast regions are observed. Micro-probe Raman measurements revealed that the dark regions dominantly observed in Figs. 2(a), 2(c), and 2(d) are crystal, while bright regions dominant in Fig. 2(b) are not crystal. These results indicate that layer exchange crystallization occurs for the samples shown in Figs. 2(a), 2(c), and 2(d), while it does not proceed for the sample shown in Fig. 2(b). EBSD measurements revealed that the grown layers for Fig. 2(d) consisted of (111)-oriented large-grains (≥10 μm). On the other hand, grown layers for Figs. 2(a) and 2(c) consisted of randomly-oriented small-grains (1-3 μm). Here, we examined the Nomarski micrographs of a no-grown Si0.5Ge0.5 sample (diffusion barrier thickness: 5 nm), shown in Fig. 2(b). It is found that nuclei are formed for the Si0.5Ge0.5 sample, though lateral growth does not proceed from the nuclei. From this finding, it is speculated that for the Si0.5Ge0.5 sample (diffusion barrier thickness: 5 nm), (111)-oriented nucleation occurs at Au/SiO2 interface. However, lateral growth does not proceed even after long time annealing. Thus, layer-exchange is not observed. It is suggested that lateral crystallization in GIC is retarded by Si introduction. This consideration triggers an idea that (111)-oriented large-grains can be obtained even for the Si0.5Ge0.5 sample by generating lateral growth from nuclei. Thus, we examine annealing at a higher temperature of 300°C. A Nomarski micrograph of Si0.5Ge0.5 sample (diffusion barrier thickness: 5 nm) after annealing at 300°C for 50 h is shown in Fig. 3(a). Micro-probe Raman measurements reveled layer-exchange crystallization in the entire area. The crystal structures of the grown layer are examined by EBSD measurements. The result is shown in Fig. 3(b), which reveals (111)-oriented large-grains (≥10 μm). As a result, quasi-single crystal SiGe is realized on insulator. This technique will facilitate realization of advanced flexible electronics. ACKNOWLEDGEMENT Part of this work was supported by JSPS Core-to-Core Program, A. Advanced Research Networks. References [1] J.-H. Park et al., Appl. Phys. Lett. 103, 082102 (2013). [2] J.-H. Park et al., Jpn. J. Appl. Phys. 53, 020302 (2014). [3] J.-H. Park et al., Appl. Phys. Lett. 104, 252110 (2014). Figure 1

Introduction Formation of crystalline GeSn film on insulator with high Sn concentration exceeding thermal equilibrium solid-solubility is strongly expected to realize high-speed thin film transistors. To explore non-thermal equilibrium processing [1], we examined crystallization of amorphous-GeSn (a-GeSn) with various modulated Sn concentration by pulsed laser annealing (PLA). In the present study, we focus on the influence of the Sn concentration on crystallization of a-GeSn by PLA. Experimental Procedure Schematic sample structure and PLA conditions are shown in Fig.1. A-Ge1-xSnx (0≦x≦0.2) films (thickness: 100 nm) were deposited on quartz substrates by a molecular beam technique. These samples were irradiated with a pulsed laser (energy : 10 - 230 mJ/cm2, pulse period : 1 sec, pulse number : 100 shot). The laser annealed regions were analyzed by Nomarski microscopy and Raman scattering spectroscopy. Results and Discussion Nomarski micrograph and Raman spectra of Ge0.8Sn0.2 samples before and after PLA with various energy are summarized in Fig. 2. In the samples after PLA, the contrast-changed regions were observed, compared with the as-deposited sample. Here, the contrast becomes stronger with increasing energy from 50 mJ/cm2 to 170 mJ/cm2, and finally the GeSn layer was damaged for energy of 230 mJ/cm2. Raman spectra reveales that Ge0.8Sn0.2 is crystallized on insulating substrates by 50 - 170 mJ/cm2 PLA. The process-window to achieve crystalline GeSn is summarized in Fig. 3(a), where the energy for starting crystallization and the energy just before damaging are indicated as Ecryst. and Edamage , respectively. Substitutional Sn concentration estimated from shift of Ge-Ge peak obtained by Raman measurements is shown in Fig. 3(b). The process window necessary for crystallization is significantly expanded by introducing Sn, i.e. 16 mJ/cm2 for Ge, ~ 130 mJ/cm2 for GeSn. High Sn concentration exceeding thermal equilibrium solid-solubility is obtained by PLA, for all GeSn samples. Interestingly, for samples with initial Sn concentration of 5 % and 10 %, almost all Sn atoms are incorporated into substitutional site, while for 20 % sample, only half of Sn atoms are incorporated into substitutional site. The detailed physics will be discussed in the presentation. References [1] M. Kurosawa, et al., Appl. Phys. Lett. 104, 061901 (2014). Figure 1

Low-temperature (≤200°C) formation of GeSn (substitutional Sn concentration: >8%) films on insulator is desired to realize high-speed thin film transistors (TFTs) and high-efficiency optical devices on flexible plastic substrates (softening temperature: ∼200°C). This is because GeSn (substitutional Sn concentration: >8%) has higher carrier mobility than Si and Ge due to the direct-transition energy band structure with smaller effective mass of carriers.

Low temperature (≤500°C) formation of n-type crystalline Ge films on insulator is required to achieve the next-generation large-scale integrated circuits (LSI), where optical functions are merged. This is because n-type Ge shows high-efficiency optical functions owing to high electron population in the Γ band.

We explore magnetic tunnel junctions consisting of Co60Fe40/AlOx/Co2FeSi trilayers on Si(111) by room-temperature molecular beam epitaxy. Even for the all room-temperature fabrication processes, the Co2FeSi layer includes L21-ordered structures. We demonstrate reproducible tunneling magnetoresistance ratios of ~ 44% and ~ 28% at 30 K and 300 K, respectively. Assuming the same room-temperature spin polarization (P) of CoFe alloys, P for Co2FeSi grown at room temperature is larger than that for D03-Fe3Si grown at 130 °C.

High-quality Ge-on-insulator (GOI) structures are essential to realize next-generation large-scale integrated circuits, where GOI is employed as active layers of functional devices, as well as buffer layers for epitaxial growth of functional materials. In line with this, in-depth analysis of crystallinity of rapid-melting-grown GOI is performed. Structural and electrical measurements combined with a thinning technique reveal that the crystallinity of GOI (500 nm thickness) is very high and uniform in-depth direction, where high hole mobility (~ 1000 cm 2 /V s) is achieved throughout the grown layers. These findings open up a possibility of application of rapid-melting-grown GOI to various advanced functional devices.

We demonstrate the (111)-oriented Ge-on-Insulator (GOI) formed by Ge epitaxial growth on a Si(111) and the layer transfer technique. The two-step growth manner, involving low-temperature growth of a thin Ge layer and subsequent high-temperature growth of a thick Ge layer, enables us to obtain high-quality tensile-strained epitaxial Ge(111) on Si(111). It is found that the strain amount straongly depends on the growth temperatures and we find an optimal growth temperature. We also developed a chemical mechanical polishing (CMP) method modified for Ge, offering the ultra-smooth Ge(111) surface. The polished epitaxial Ge is bonded on a SiO2/Si, followed by the selective etching of Si and the final CMP of Ge. As a result, we achieve the high-quality 200-nm-thick tensile-strained Ge(111)-OI with an ultra-smooth surface, on which, furthermore, we demonstrate the growth of an epitaxial metallic silicide for the metal source/drain in spintronic devices as well as advanced Ge channel devices.

We have explored an effect of the interface resistance of Fe3Si/n+-Ge Schottky-tunnel contacts on spin accumulation created electrically in n-Ge. Using the Schottky-tunnel contacts with a relatively high interface resistance, we can clearly detect spin-accumulation signals in n-Ge even at room temperature, meaning that the use of highly resistive Schottky tunnel contacts is effective to electrically create large spin accumulation. Since such highly resistive source and drain electrodes are not available for next-generation Ge-based spintronic applications with ultra-low power consumption, the development of highly spin-polarized spin injectors such as half-metallic materials is essential from now on.

In rapid-melting-crystallization of network Ge-on-insulator (GOI), coalescence of growth-fronts inevitably occurs. To clarify crystallinity of the coalesced regions of two growth-fronts in GOI stripes, scanning electron microscopy and transmission electron microscopy analyses are performed. These analyses reveal that lattice planes of two growth-fronts coherently align without strains for short growth-distance (≤ 5 μm). The lattice planes at growth-fronts start to tilt gradually for growth-distance above 5 μm. For intermediate growth-distance (5–150 μm), slightly-tilting lattice-planes coherently align without generating any defects, where locally-distributed strains are induced in the coalesced regions. On the other hand, for long growth-distance (≥ 150 μm), grain-boundaries are generated in coalesced regions, and the locally-distributed strains are relaxed. The coherent lattice-alignment for growth-distance below 150 μm is attributed to atomic reordering in the coalesced regions, where coalescence occurs at high temperatures around the solidification point of Ge.

Dynamics in rapid-melting growth are analyzed by using Si-segregation phenomena in SiGe-on-insulator (SGOI). To clarify growth-stream and growth-velocity, SiGe profiles in SGOI network and stripe structures are investigated. Based on 2-dimensional Si-concentration mapping for SGOI network, visualization of routes of growth fronts becomes possible. In addition, analysis of Si concentration profiles in SGOI stripes enables evaluation of growth velocity. It is clarified that growth velocity increases by 15 times with increasing growth distance for SGOI stripe with 500 μm length. These techniques are useful to understand detailed kinetics in rapid-melting growth.

For high-performance spin injectors in silicon (Si)-based spintronic applications, we have explored the growth technique of quaternary Co-based Heusler-compound Co2FeSi0.5Al0.5 on Si(111) by using low-temperature molecular beam epitaxy (LTMBE). In our previous study, Al co-deposition induced an interfacial reaction between Co2FeSi1 − xAlx and Si. Here, we dramatically improve the Co2FeSi0.5Al0.5/Si heterostructures by introducing a nonstoichiometric LTMBE technique. Atomically smooth Co2FeSi0.5Al0.5/Si heterointerfaces and L21-ordered Co2FeSi0.5Al0.5 films are simultaneously achieved. Even in as-grown conditions, the magnetic properties of the Co2FeSi0.5Al0.5 layers are nearly equivalent to those of the heat-treated ones reported on MgO. This study gives important knowledge to realize the optimized highly spin-polarized ferromagnet/Si heterointerfaces for next-generation Si-based spintronic devices.

High-speed fully depleted thin-film transistors (TFTs) for low-power consumption are required for next-generation electronics, such as three-dimensional large-scale integrated circuits and advanced system-in-displays. For this purpose, high-carrier-mobility semiconductor thin-films (thickness: ≤∼50 nm) on insulator structures should be fabricated under low-temperature processing conditions (≤500 °C). To achieve this, solid-phase crystallization of amorphous GeSn (a-GeSn) with low Sn concentration (2%) is investigated for a wide range of film thicknesses (30 − 200 nm), where thin a-Si underlayers (thickness: 0 − 20 nm) are introduced between a-GeSn films and substrates. GeSn is polycrystallized by annealing at 450 °C, keeping Si underlayers amorphous. Crystal grains of almost identical sizes are obtained for GeSn thicknesses of 30 − 50 nm, though grain sizes significantly decrease for thicknesses exceeding 50 nm owing to enhanced bulk nucleation. A detailed analysis of GeSn films (thickness: 50 nm) reveals that grain sizes are decreased by introducing a-Si underlayers (thickness: 3 − 20 nm), e.g., from ∼10 μm to 2 − 3 μm. This phenomenon is attributed to the change in dominant nucleation sites from the interface to the bulk, which significantly decreases grain-boundary scattering of carriers through a decrease in the barrier heights at grain boundaries. As a result, a high carrier mobility of 200 − 300 cm2/V s is realized for GeSn thin-films (thickness: 30 − 50 nm) grown with a-Si underlayers. The mobility (200 − 300 cm2/V s) is the largest ever reported data for Ge and GeSn thin-films (thickness: 30 − 50 nm) grown at low temperatures (≤500 °C). This technique will facilitate the realization of high-speed fully depleted TFTs for next-generation electronics.

To develop a new low-temperature crystallization technique, annealing characteristics of a-GeSn/Si (100) structures are investigated. It is revealed that epitaxial growth accompanying Si-Ge mixing is generated at temperatures in the liquid-solid coexisting region of the Ge-Sn system. The annealing temperature necessary for epitaxial growth is significantly decreased by increasing annealing time and/or Sn concentration. Consequently, epitaxial growth at 300°C becomes possible. These findings are expected to be useful to realize next-generation large-scale integrated circuits, where various multi-functional devices are integrated.

We have investigated crystal quality of Co2(Mn1–xFex)Si (CMFS) epitaxially grown on Ge(111) by using Rutherford backscattering spectrometry and axial ion channeling technique. It was found that the CMFS/Ge and Co2FeSi (CMFS with x = 1)/Ge have larger static atomic displacement than Fe based ternary Heusler alloy Fe2MnSi and Fe2CoSi/Ge(111). Quaternary alloys may be affected by increase of mixing entropy. Significant disordering at the interface of 0.75CMFS was found, and discussed on basis of thermodynamics. (© 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Low-temperature (≤250oC) formation of orientation-controlled large-grain (>10 μm) poly-SiGe on amorphous insulator is essential to realize flexible electronics. In line with this, metal-induced crystallization of SiGe is investigated. By employing Au and Sn as catalysts, SiGe crystallization at 250oC and 150oC, respectively, becomes possible. Moreover, a technique for formation of orientation-controlled large-grain crystals is examined by modulation of nucleation in gold-induced crystallization. This achieves selectively (100)- or (111)-oriented large-grain (≥20 μm) crystals on amorphous insulators. This technique is expected to facilitate integration of advanced functional devices onto flexible substrates.

INTRODUCTION To break through the scaling limit of Si-LSIs, development of functional materials becomes essential. GeSn is a big candidate for this purpose, because GeSn provides direct energy-band gap and very light carrier effective-mass [1,2]. In line with this, development of a formation technique of high-quality GeSn is desired. Our approach for formation of high-quality GeSn is utilization of liquid-phase reaction. To induce liquid-phase crystallization at low temperatures, we propose to employ a-Ge/Sn stacked structures deposited on c-Ge as a starting material. To examine this idea, in the present study, we investigate growth characteristics of a-Ge/Sn/c-Ge stacked structures.

High-quality crystalline Ge thin films on low-cost glass substrates are desired to reduce the fabrication cost of high-efficiency tandem solar cells. We applied an Al-induced crystallization technique to amorphous-Ge films (50-nm thickness) on SiO 2 glass substrates. The annealing temperature of the sample strongly influenced the grain size and the crystal orientation in the grown polycrystalline Ge layers: low annealing temperatures resulted in large grains and high (111)-orientation fractions. As a result, annealing at 325 °C provided 98% (111)-oriented grains with average diameters of 30 μm. Moreover, the grown Ge layers could be used as an epitaxial template for chemical vapor deposition. This large-grained Ge film on a SiO 2 substrate appears promising for use as a Ge light-absorbing layer, as well as an epitaxial buffer layer for group III–V compound semiconductors.

The low-temperature-crystallization effects of soft X-ray irradiation on the structural properties of amorphous Si and amorphous Ge films were investigated. From the differences in crystallization between Si and Ge, it was found that the effects of soft X-ray irradiation on the crystallization strongly depended on the energy band gap and energy level. The crystallization temperatures of the amorphous Si and amorphous Ge films decreased from 953 K to 853 K and 773 K to 663 K, respectively. The decrease in crystallization temperature was also related to atoms transitioning into a quasi-nucleic phase in the films. The ratio of electron excitation and migration effects to thermal effects was controlled using the storage-ring current (photon flux density). Therefore, we believe that low-temperature crystallization can be realized by controlling atomic migration through electron excitation.

We present two important technologies for silicon-germanium (SiGe) spintronics. First, we show high-quality epitaxial growth of bcc-type ferromagnetic alloys on Si or Ge with atomically controlled interfaces. Second, we establish electrical spin injection and detection across the high-quality interfaces in Si- or Ge-based devices. Combining these technologies with a metal-oxide-semiconductor field-effect transistor structure, we can demonstrate room-temperature detection of spin accumulation and control the magnitude of the spin signals. These novel and interesting results are expected to build the basis of a key technology toward developing next-generation SiGe spintronic devices.

Research and development for new semiconductor devices which enable ultrahigh speed operation, ultralow power dissipation, and/or multi-functional operation are strongly required to overcome a scaling limit of the complementary metal-oxide-semiconductor (CMOS) performance. Thus, Si-based heterostructure technologies have been widely developed over the last quarter century [1]. The hetero-epitaxial growth of III-V semiconductors and ferromagnetic Heusler alloys is the typical example, which achieves optical emission and spin injection on Si and Ge substrates [2-6]. In order to create multi-functional large scale integrated circuits (LSI), such new materials should be stacked on the group-IV semiconductor platform with high carrier mobilities. Consequently, development of high quality Ge-on-insulator (GOI) structures becomes essential. In line with this, we have been developing SiGe mixing triggered rapid-melting growth [7-8]. This achieves defect-free Ge and SiGe single crystals on insulating substrates. In addition, hybrid-formation of (100), (110), and (111) GOI is achieved on (100) Si platform by using metal-induced crystallization methods for Si micro-seed formation. Here, we emphasize that such hybrid-structures are so-called artificial crystals, because no single-crystalline substrates have been used to initiate Ge rapid-melting growth. The present paper reviews our recent progress in this novel growth technique [7-18]. Main subjects to be discussed in this symposium are as follows

Using low-temperature molecular beam epitaxy (LTMBE), we demonstrate high-quality heterointerfaces consisting of CoFe alloys and germanium (Ge) with a good atomic matching at the (111) plane. Electrical properties of the atomically matched CoFe/p-Ge(111) junctions with the area of (S) < ~10 μm2 clearly show the suppression of the Fermi-level pinning (FLP) effect, similar to the features of the atomically matched Fe3Si/p-Ge(111) junctions with S < ~10 μm2 in our previous work. This means that the suppression of FLP is independent on a kind of metals. As a result, we conclude that the formation of the atomically matched metal/Ge interfaces with almost no defects is important to suppress FLP.

INTRODUCTION SiGe-on-insulator and Ge-on-insulator structures are essential to realization of advanced LSIs. Recently, we developed SiGe mixing triggered liquid-phase epitaxy (LPE) of a-Ge [1,2], which achieved high quality giant Ge single crystals (length: ~1cm) on insulating substrates [3]. In course of the study, we encountered a phenomenon that large grain Ge single crystals (~5 m) grew on insulating substrates without any seed [2]. On the other hand, SiGe has solidification-completing temperatures significantly different from solidification-initiating temperatures in melting growth. Thus, longer growth times are expected for SiGe compared with pure Ge. This triggered an idea that much larger crystal grains should be obtained, if a-SiGe films were melt-grown instead of a-Ge. To examine this idea, we investigate rapid-melting growth of a-SiGe on insulating substrates without any seed.

A low-temperature formation technique of Sn-doped Ge on insulator has been investigated by aluminum-induced crystallization using a-GeSn/Al stacked structures. For a-GeSn films (Sn concentration: 2%), the layer-exchange growth temperature is significantly decreased compared with a-Ge, which enables low temperature growth at 250°C. At such a low temperature, bulk nucleation of GeSn in Al layers is significantly suppressed, and (100)-oriented interface nucleation becomes dominant. On the other hand, growth rate becomes high by Sn-doping effects. As a result, formation of (100)-oriented large-grain (>10 μm) Sn-doped Ge (Sn concentration: 2%) crystals on insulating substrates becomes possible at a low temperature (250°C). This technique will be useful to realize advanced flexible electronics.

For spintronic applications compatible with silicon (Si) large scale integrated circuits, we have so far developed the growth technique of a Co-based Heusler-compound film, Co2FeSi, on Si by using low-temperature molecular beam epitaxy. In this study, we explore an addition technique of a fourth element, Al, to the Co2FeSi films in order to tune the number of the valence electrons and to realize the high-performance spintronic devices. We can demonstrate L21-ordered Co 2 F e S i 0.5 A l 0.5 films using Al co-deposition although 4-nm-thick reaction layers are formed at the interface. A possible mechanism of the epitaxial growth of quaternary Co 2 F e S i 1 − x A l x films on Si is discussed.

We have investigated perfection of atomic rows on iron-based Heusler alloy films on Ge(111) planes by using ion channeling technique in order to find the dominant factors for the perfection. Fe 3 Si/Ge(111) and Fe 2 CoSi/Ge(111) have a high quality of atomic rows at the heterointerface like that of perfect crystals. Fe 3−x Mn x Si/Ge(111) ( x = 0.84, 0.72 and 0.36) interfaces have imperfection of atomic rows which may be controlled by both the lattice mismatch with the Ge substrate and the Mn–Si pairs due to the site disorder in the film with the Mn content x > 0.75. Analysis of axial channeling parameters employed in this study is very useful for quantitative evaluation of perfection of atomic rows at the heterointerface.

Liquid-phase epitaxial growth of Ge islands on insulator (GOI) using Ni-imprint-induced Si (1 1 1) micro-crystal seeds (∼1 μmϕ) is proposed. As a result, single-crystalline GOI (1 1 1) structures with large area (∼10 μmϕ) are realized. The transmission electron microscopy observations reveal no dislocation or stacking fault in the laterally grown regions. Moreover, the Raman measurements show that the tensile strain (∼0.2%) which enhances the carrier mobility is induced in the growth regions. This new method can be employed to realize the multi-functional SiGe large scale integrated circuits.

The lateral liquid-phase epitaxy of Ge-on-insulator (GOI) using Si seeds has been investigated as a function of the Si-seed orientation and the growth direction. Giant single-crystalline GOI structures with ∼200 μm length are obtained using Si(1 0 0), (1 1 0), and (1 1 1) seeds. The very long growth is explained on the basis of the solidification temperature gradient due to Si–Ge mixing around the seeding area and the thermal gradient due to the latent heat around the solid/liquid interface at the growth front. In addition, growth with rotating crystal orientations is observed for samples with several growth directions. The rotating growth is explained on the basis of the bonding strength between lattice planes at the growth front. This rotating growth does not occur in any direction for (1 0 0) orientated seeds. Based on this finding the mesh-patterned GOI growth with a large area (250 μm × 500 μm) is demonstrated.

We comprehensively investigate Al-induced crystallization (AIC) of Si to achieve (0 0 1) and (1 1 1)-oriented Si films on quartz substrates. These phenomena are systematically explained by ‘preferential interfacial-nucleation model’ considering the nucleation sites and the phase transition of the interfacial Al oxide layers. Moreover, we demonstrate the lateral liquid phase epitaxy of Ge by using the orientation-controlled AIC-Si films as crystal seed. This technique enables high quality hetero-epitaxy of SiGe and Ge on transparent insulating substrates.

We have investigated the Si-seeding rapid-melting process and demonstrated the formation of giant Ge stripes with (100), (110), and (111) orientations on Si (100), (110), and (111) substrates, respectively, covered with SiO2films. We revealed that crystallization is triggered by Si-Ge mixing in the seeding regions in this process. Based on this mechanism, we have proposed a novel technique to realize orientation-controlled Ge layers on transparent insulating substrates by using Si artificial micro-seeds with (100) and (111)-orientations. This achieved epitaxial growth of single crystalline (100) and (111)-oriented Ge stripes on quartz substrates. The Ge layers showed a high hole mobility exceeding 1100 cm2/Vs owing to the high crystallinity.

We have examined the LMOKE of some Heusler alloy films Fe4Si, Fe3Si, Fe2CoSi, Fe2MnSi (21 at and 9 at.%Mn), Co2FeSi epitaxially grown on Ge(111) and found that Fe3Si, Fe4Si and Fe2CoSi films have larger Kerr rotation and smaller coercive fields than the amorphous Fe film and that they may be promising materials for magnetophotonic applications.

High-quality orientation-controlled Ge on insulator (GOI) structures are essential to realize high-performance thin-film transistors (TFTs) and epitaxial templates for multifunctional 3-dimensional large-scale integrated circuits (3D-LSIs). We have investigated the Si-seeding rapid-melting process and demonstrated formation of giant Ge stripes with (100), (110), and (111) orientations on Si (100), (110), and (111) substrates, respectively, covered with SiO2 films. We revealed that crystallization is triggered by Si-Ge mixing in the seeding regions in this process. Based on this mechanism, we have proposed a novel technique to realize orientation-controlled Ge layers on transparent insulating substrates by using Si artificial micro-seeds with (100) and (111)-orientations. This achieved epitaxial growth of single crystalline (100) and (111)-oriented Ge stripes on quartz substrates. The transmission electron microscopy observations revealed no-defects in the laterally grown Ge regions. The Ge layers showed a high hole mobility exceeding 1100 cm2/Vs owing to the high crystallinity. This novel SiGe mixing-triggered growth technique opens up the possibility of the next-generation TFTs and multifunctional 3D-LSIs.

High-speed thin-film transistors (TFTs) are required to develop the next generation of electronics, such as three-dimensional large-scale integrated circuits and advanced system-in-displays. For this purpose, high-carrier-mobility semiconductor films on insulator structures should be fabricated with low-temperature processing conditions (≤500 °C). To achieve this, we investigate solid-phase crystallization of amorphous-GeSn (a-GeSn) films (Sn concentration: 2% and thickness: 50–200 nm) on insulating substrates, where thin a-Si under-layers (thickness: 0–20 nm) are introduced between a-GeSn films and insulating substrates. The GeSn films are polycrystallized by annealing (450 °C, 20 h) for all samples irrespective of a-GeSn and a-Si thickness conditions, while the Si films remain amorphous. Analysis of crystal structures of GeSn films (thickness: 50 nm) reveals that grain sizes decrease from ∼10 μm to 2–3 μm by the introduction of a-Si under-layers (thickness: 3–20 nm). This phenomenon is attributed to the change in dominant nucleation sites from the interface to the bulk, which significantly decreases grain-boundary scattering of carriers through a decrease in the barrier heights at grain boundaries. Bulk-nucleation further becomes dominant by increasing the GeSn film thickness. As a result, a high carrier mobility of ∼550 cm2/V s is realized for GeSn films (thickness: 100 nm) grown with a-Si under-layers. This mobility is the largest among ever reported data for Ge and GeSn grown on an insulator. This technique will facilitate realization of high-speed TFTs for use in the next generation of electronics.At the request of the authors, this article is being retracted effective 11 July 2018.High-speed thin-film transistors (TFTs) are required to develop the next generation of electronics, such as three-dimensional large-scale integrated circuits and advanced system-in-displays. For this purpose, high-carrier-mobility semiconductor films on insulator structures should be fabricated with low-temperature processing conditions (≤500 °C). To achieve this, we investigate solid-phase crystallization of amorphous-GeSn (a-GeSn) films (Sn concentration: 2% and thickness: 50–200 nm) on insulating substrates, where thin a-Si under-layers (thickness: 0–20 nm) are introduced between a-GeSn films and insulating substrates. The GeSn films are polycrystallized by annealing (450 °C, 20 h) for all samples irrespective of a-GeSn and a-Si thickness conditions, while the Si films remain amorphous. Analysis of crystal structures of GeSn films (thickness: 50 nm) reveals that grain sizes decrease from ∼10 μm to 2–3 μm by the introduction of a-Si under-layers (thickness: 3–20 nm). This phenomenon is attributed to the...