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Nanoimprint lithography (NIL) has been received attention as an alternative lithographic technology, which can fabricate fine patterns of semiconductor devices at low cost, by transferring fine pattern of a template on to a resist layer by physical contact of template and resist followed by the resist curing. For more than a decade, we have been developing Jet and Flash Imprint Lithography (J-FIL) technology and challenging critical issues such as defect density, overlay, and throughput. J-FIL is an efficient process for transferring template pattern having large variations in pattern density. However, it has the intrinsic limitation of lower throughput due to resist dispensing time prior to imprinting of every single field on the wafer and the spreading process of resist drops, slow diffusion of bubble trapped at the resist drop-boundaries. To eliminate the above mentioned steps and improve throughput, we have developed a spin coating NIL (SCN) process in which a uniform resist layer is spin coated on the entire wafer. Identification of defect generation mechanism assuming Washburn’s model of capillary flow, has led us to optimize SCN process and thus achieving a higher throughput with lower defect density as compared to that of the J-FIL process. We will show the defect density and throughput performance of SCN process, and the possibility of introducing SCN in device production.

A low cost alternative lithographic technology is desired to cope with the challenges in decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the viable candidates. [1][2][3] NIL has been a promising solution to overcome the cost issue associated with expensive process and tool of multi patterning and EUVL. The challenges of NIL implementation for mass-production are overlay, defects, throughput, template life, and template patterning. The overlay and defects must satisfy the requirements of the products applied. The throughput needs to provide adequate cost of ownership (CoO). Since NIL is a contact process, its template damage by the particles on a wafer is inescapable and a longer template life is required for mass production.[4]-[10] In our previous study, we have reported that the hp2xnm NIL process performance is getting closer to the requirement for the high volume manufacturing. We focused on the process overlay accuracy and demonstrated dramatic reduction of process overlay error by using CVA(controlled viscosity alignment) and HODC(high order distortion control) function of FPA-1200 NZ2C. [11] Currently, we have further developed a nanoimprint lithography (NIL) technology including NIL system, template, and resist process for half pitch 14 nm direct pattering. The hp14 nm template was fabricated by a self-aligned double patterning (SADP) on a template. Using this template, we fabricated hp 14 nm dense Si lines with a depth of 50 nm on a 300 mm wafer. In this paper, we report on the latest lithography performance of NIL including hp14nm pattering with single mask exposure.

We developed a nanoimprint lithography (NIL) technology including NIL system, template and resist process for half pitch (hp) 14 nm direct pattering. The latest NIL system NZ2C shows the mix and match overlay (MMO) of 3.4 nm ( $3\sigma$ ) and the template life around 125 lots. Throughput of 80 wafers per hour (wph) was demonstrated using throughput enhancement solutions, such as gas permeable spin-on-carbon (GP-SOC) and multi field dispense (MFD). The hp 14 nm template was fabricated by a self-aligned double patterning (SADP) on a template. Using this template, we fabricated hp 14 nm dense Si lines with a depth of 50 nm on a 300 mm wafer.

A low cost alternative lithographic technology is desired to cope with the challenges in decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the viable candidates.[1][2][3] NIL has been a promising solution to overcome the cost issue associated with expensive process and tool of multi patterning and EUVL. NIL is a simple technology and is capable of forming critical patterns easily. On the other hand, the critical issues of NIL are defectivity, overlay, and throughput. In order to introduce NIL into the High Volume Manufacturing (HVM), it is necessary to overcome these three challenges simultaneously.[4]-[10] In our previous study, we have reported improvement in NIL overlay, defectivity and throughput by the optimization of resist process on a pilot line tool, FPA-1200 NZ2C. In this study, we report recent evaluation of the NIL performance to judge its applicability in semiconductor device HVM. We have described that the NIL is getting closer to the target of HVM for 2x nm half pitch.[8]Defectivity level below 1pcs/cm2 has been achieved for the 2x nm half pitch L/S. The overlay accuracy of the test device is being improved down to 6nm or lower by introducing high order distortion correction.

Nanoimprint lithography (NIL) is a candidate of alternative lithographic technology for memory devices. We are developing NIL technology and challenging critical issues such as defectivity, overlay, and throughput . NIL material is a key factor to support the robust patterning process. Especially, resist material can play an important role in addressing the issue of the total throughput performance. The aim of this research is to clarify key factors of resist property which can reduce resist filling time and template separation time . The liquid resist is filled in the relief patterns on a quartz template surface and subsequently cured under UV radiation. The filling time is a bottleneck of NILthroughput. We have clarified that the air trapping in the liquid resist is critical. Based on theoretical study, we have identified key factors of NIL-resist property. These results have provided a deeper insight into resist material for high throughput NIL.

A low cost alternative lithographic technology is desired to meet the decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the candidates for alternative lithographic technologies.[1][2][3] NIL has such advantages as good resolution, critical dimension (CD) uniformity and low line edge roughness (LER). On the other hand, the critical issues of NIL are defectivity, overlay, and throughput. In order to introduce NIL into the HVM, it is necessary to overcome these three challenges simultaneously.[4]-[12] In our previous study, we have reported a dramatic improvement in NIL process defectivity on a pilot line tool, FPA-1100 NZ2. We have described that the NIL process for 2x nm half pitch is getting closer to the target of HVM.[12] In this study, we report the recent evaluation of the NIL process performance to judge the applicability of NIL to memory device fabrications. In detail, the CD uniformity and LER are found to be less than 2nm. The overlay accuracy of the test device is less than 7nm. A defectivity level of below 1pcs./cm2 has been achieved at a throughput of 15 wafers per hour.

A low cost alternative lithographic technology is desired to meet with the decreasing feature size of semiconductor devices. Nanoimprint lithography (NIL) is one of the candidates for alternative lithographic technologies. NIL has advantages such as good resolution, critical dimension (CD) uniformity and smaller line edge roughness (LER). 4 On the other hand, NIL involves some risks. Defectivity is the most critical issue in NIL. The progress in the defect reduction on templates shows great improvement recently. In other words, the defect reduction of the NIIL process is a key to apply NIL to mass production. In this paper, we describe the evaluation results of the defect performance of NIL using an up-to-date tool, Canon FPA-1100 NZ2, and discuss the future potential of NIL in terms of defectivity. The impact of various kinds defects, such as the non-filling defect, plug defect, line collapse, and defects on replica templates are discussed. We found that non-fill defects under the resist pattern cause line collapse. It is important to prevent line collapse. From these analyses based on actual NIL defect data on long-run stability, we will show the way to reduce defects and the possibility of NIL in device high volume mass production. For the past one year, we have been are collaborating with SK Hynix to bring this promising technology into mainstream manufacturing. This work is the result of this collaboration.

Technologies for pattern fabrication using Nanoimprint lithography (NIL) process are being developed for various devices. NIL is an attractive and promising candidate for its pattern fidelity toward 1z device fabrication without additional usage of double patterning process. Layout dependent hotspots become a significant issue for application in small pattern size device, and design for manufacturing (DFM) flow for imprint process becomes significantly important. In this paper, simulation of resist spread in fine pattern of various scales are demonstrated and the fluid models depending on the scale are proposed. DFM flow to prepare imprint friendly design, issues for sub-20 nm NIL are proposed.

Nanoimprint lithography under helium exposure plays an important role in realizing rapid resist spreading. It is expected that the reduction in the surface tension of the resist due to the diffusion of helium would have an impact on the spreading behavior of the resist. By assuming van der Waals potential, the surface tension of the resist under helium exposure is estimated to be reduced by 70%. In our experiment, we obtain an 83% reduction in the surface tension of a resist under helium exposure by evaluating the meniscus shape at the corner of a rectangular imprinted area after UV curing. Furthermore, the C/O composition ratio of the resist after UV curing is found to change due to the exposure. Our study confirms that helium strongly affects the surface tension of the resist. The result also suggests the possibility of the supercritical fluidic behavior of helium in the resist. The resist spreading velocity can be increased by 2.5 times by helium exposure.

The newest GIS is being reduced in size due to advances in arrester performance and reduction of impulse test voltage for specifications. Field strength of the inner surface for the GIS tank is being strengthened more than ever; for this, it is necessary that the design work consider particles included in the GIS. When GCB and DS are opened, residual DC voltage occurs at the conductor between the GCB and DS. Movement of particles under DC voltage is known to differ from that under AC voltage. It is very important to know particle movement under DC voltage, even if the GIS is for AC use. Therefore, this paper deals with particle-levitation under DC voltage in SF6 gas. Effects of polarity and vibration were confirmed for levitation of a particle on an insulated coating electrode. An aluminum particle (φ0.25×L3) on a sheath of 0.5MV/m did not levitate until a 6.5G oscillation acceleration was reached under a single-polarity DC voltage. On the other hand, the particle levitated at about a 2G oscillation acceleration under a reversed polarity DC voltage. Moreover, oscillation acceleration of initial levitation for a large size GIS model was almost equal with that of fundamental experiments.

GIS is compacted by progress of arrester and reduction of impulse test voltage for specifications recently. Since field strength of inner surface for GIS tank is more strengthened than ever, it is more necessary that included particle in GIS is taken into consideration. When GCB and DS are opened, residual dc voltage occurs at conductor between GCB and DS. It is well known that movement of particle under ac voltage is different from that of dc voltage. Therefore it is very important that particle movement under dc voltage is taken into consideration, even if GIS is for ac.From the above, this paper deals with firefly phenomenon of particle under dc voltage in SF6 gas. It investigates that prevention of fire fly phenomenon by electric field strength of conductor. And the minimum electric field strength to continue firefly phenomenon of particle is made clear. Then the breakdown voltage with firefly particle is compared with that of particle; with a minute gap, fixed to conductor.

This paper proposes a new type of automatically tuned filter for HVDC Converter Station. The proposed method is largely based on the existing and reliable technologies, i.e. oil which is the most common insulation medium and the electromagnetic shield and coil configuration which is used for the air-core reactor.The automatically tuning is achieved by changing the mutual inductance by opening and closing two or more cover coils (short-circuit coil) between the air-core coil and electromagnetic shield. The basic performance was confirmed through the shop tests of a prototype reactor and a small scale automatically tuned filter system.

Pyrolysis-gas chromatography of alternating carbon monoxide-olefin co- and terpolymers was studied. Ethylene (E) and/or propylene (P)carbon monoxide (CO) co- and terpolymers (ECO, PCO and EPCO, respectively) and ethylene-styrene (S)carbon monoxide terpolymers (ESCO) were prepared by palladium catalyst and pyrolyzed at 550 °C for 10 s. Various linear ketones, cyclic compounds and ketoesters were identified among the degradation products of ECO. The product distribution supports the hypothesis that chain scissions and cyclization reactions take place at the same time in the thermal degradation of this copolymer. The pyrolyzed products of the PCO copolymer are explained as the methyl derivatives of the corresponding products of the ECO copolymer. The products of the ethylene-based terpolymers are divided into three categories; that is, those formed from ECO/ECO, ECO/P(S)CO and P(S)CO/P(S)CO dyads. The EPCO1 sample, which contained 31% of PCO unit, gave the pyrolyzed products from the PCO/PCO dyad in a very small amount. The ESCO terpolymers showed somewhat different degradation behavior from that of styrene–carbon monoxide copolymer.

Directed self-assembly (DSA) of block copolymers (BCPs) is a promising method for producing the sub-20nm features required for future semiconductor device scaling, but many questions still surround the issue of defect levels in DSA processes. Knowledge of the free energy associated with a defect is critical to estimating the limiting equilibrium defect density that may be achievable in such a process. In this work, a coarse grained molecular dynamics (MD) model is used to study the free energy of a dislocation pair defect via thermodynamic integration. MD models with realistic potentials allow for more accurate simulations of the inherent polymer behavior without the need to guess modes of molecular movement and without oversimplifying atomic interactions. The free energy of such a defect as a function of the Flory- Huggins parameter (χ) and the total degree of polymerization (N) for the block copolymer is also calculated. It is found that high pitch multiplying underlayers do not show significant decreases in defect free energy relative to a simple pitch doubling underlayer. It is also found that χN is not the best descriptor for correlating defect free energy since simultaneous variation in chain length (N) and χ value while maintaining a constant χN product produces significantly different defect free energies. Instead, the defect free energy seems to be directly correlated to the χ value of the diblock copolymer used. This means that as higher χ systems are produced and utilized for DSA, the limiting defect level will likely decrease even though DSA processes may still operate at similar χN values to achieve ever smaller feature sizes.

The Kii-Channel HVDC Link under construction in Japan is equipped with metallic return transfer breakers (MRTBs) in one converter station. A new MRTB for an interrupting current of 3500 A DC was developed. To interrupt a DC current, a method that produces a current zero point by superimposing a self-excited oscillatory current on a DC arc current was employed. For this purpose, a LC circuit was coupled in parallel to a SF/sub 6/ gas circuit breaker. Developing a SF/sub 6/ gas circuit breaker that has a large arc voltage drop gradient against currents permitted a large oscillatory current to be generated. A modified Mayr-type dynamic arc equation was newly presented. The DC interruption limits calculated using this equation agreed with the measured values.

Flow electrification characteristics of transformer oil were investigated by applying dc and dc/ac composite fields to both bare and covered coaxial cylinder electrode systems. For the bare electrode system, flow electrification characteristics were almost the same between positive and negative dc voltage applications and negative charges were generated for both dc and dc/ac composite voltage applications at high dc fields. For the covered electrode system, the apparent flow electrification characteristics differed between positive and negative dc voltage applications. For the former, negative charges were generated at high dc fields for both dc and dc/ac composite voltage applications, and for the latter, positive charges were always generated for both voltage applications. However, negative charge generation for the positive voltage application was attributed to the influence of negative charge generation at the bare part of the covered electrode end; the fundamental charge generation characteristics of the covered electrode showed an increase of positive charge generation by dc voltage application, and positive charge generation was accelerated by a composite ac field. © 1999 Scripta Technica, Electr Eng Jpn, 130(2): 10-17

The paper describes the development of insulation structure and enhancement of insulation reliability of 500 kV DC GIS (gas insulated switchgear). Considering problems of metallic particles and charge accumulation on spacers, the developed insulation structure of GIS consisted of three regions, i.e. the spacer, particle scavenging and nonlevitating regions. Particles could be efficiently scavenged, and the developed GIS withstood all insulation specifications with sufficient margins under the clean and particle-contaminated condition. Now, a long-term site test for one year of the 500 kV DC GIS has been continued since October in 1995.

Superconducting technology is regarded as a breakthrough to future electric power transmission because of its highly densified and large transmission capability. This paper proposes a concept of the future power system composed of various superconducting apparatuses. A prototype model system called “PROMISE (PROspective power transmission Model system Integrated under Superconducting Environment)” is constructed to prove the realization of the above concept. PROMISE is composed of a superconducting transformer (60 Hz, 6/3 kV, 1000 kVA class), superconducting fault current limiter (6 kV, 200 A class), and superconducting power cable (5 m, 6 kV, 650 A class). This paper also shows that PROMISE realized the transmission of the electric power of 3.8 kV–460 kVA (50 Hz). This is the first achievement in the world. The voltage-current synthetic test verified that PROMISE can withstand ac voltage of 6 kV while carrying ac current of 170 A (60 Hz). The ac loss of superconducting cables, the heat leak of cryostat and the core loss of the superconducting transformer are measured to estimate the transmission loss of PROMISE. These fundamental performances of PROMISE may indicate the feasibility of the future introduction of superconducting technology for electric power systems.

Nanoimprint lithography (NIL) is becoming a promising technique for fine-patterning with a lower cost than other lithography techniques. High overlay accuracy is one of the issues in NIL. Using die-by-die alignment with moire fringe detection, an NIL alignment measurement accuracy below 1 nm and an overlay accuracy below 5 nm have been reported. On the other hand, the requirement for overlay in 2020 is estimated to be 3–4 nm for dynamic random access memory, flash and logic devices. In order to make the overlay accuracy requirement qualify from the semiconductor industry, a lot of technology enhancements, such as the improvement of overlay control accuracy for NIL-tools, image placement accuracy improvement for NIL templates, mix and match technique of NIL, and other lithography tools such as immersion exposure ones, are needed. In this paper, the authors describe the evaluation of the NIL overlay performance using up-to-date NIL tools, and discuss the potentials of NIL overlay in the future. Alignment accuracy, precision, and overlay correction performance of NIL tools, NIL-to-NIL and NIL-to-optical lithography tool distortion matching performance and overlay error structure analysis, are discussed. From these analyses based on NIL overlay data, the authors discuss the possibility of NIL overlay evolution to realize the adaptation to mass production for the 1×-nm device.

Direct write electron-beam (e-beam) lithography, which has the maskless patterning capability and the quick turnaround for new device designs and design changes, has been applied to making the engineering samples for the development of the System on Chip products (SoC). Using the e-beam lithography to the multilevel interconnect metal was known to be evaluate in view of cost and throughput. In the case of the high-energy e-beam lithography, however, the backscattered electron from the metal caused a significant proximity effect. Authors evaluated the e-beam proximity effect using the accelerating voltage 50keV on some multi-level interconnect metal structures which consist in tungsten wiring, or Cu wiring. It was found that the backscattering range and the ratio of the backscattering energy to the incident energy depend on the thickness of metal, but also on the distance from the resist to the metal. Therefore authors propose a new method of evaluating e-beam lithography property, concept of "EB-tree". That indicates the wafer backscatter property that has heavy metal wiring using e-beam lithography. EB-tree shows the relations of wafer backscatter range and heavy metal thickness, ratio of the backscattering energy and heavy metal thickness. EB-tree could show wafer property cause of lower levels layout, understructure metal wiring, that must be taken into account when e-beam lithography.

SON (Silicon on Nothing) MOSFET was successfully fabricated for the first time by using ESS (Empty Space in Silicon) technique as an alternative of SOI-MOSFET. Advantage of SON structure was experimentally demonstrated. SON structure using ESS technique is appropriate for System on a Chip (SoC) applications, such as embedded trench DRAMs and digital-analog mixed devices, due to the merit that SON structure can be fabricated partially on bulk substrate.

KII Channel HVDC system, the largest HVDC system in Japan, is under construction to start operation in 2000. Due to its large capacity and new test items, there have been several efforts in production and testing. In this report we introduce the tests of the thyristor valve for the KII Channel 1st stage project, explain "tests with transient forward voltage during the recovery period" which was to be added, and "nonperiodic firing test" which was to be the provided test conditions.

±500kV DC transmission between Honshu island and Shikoku island in Japan will be operated at the beginning of the next century. High voltage DC-Gas Insulated Switchgear (DC-GIS) equipped in the DC-AC converter station has been developed. One of considerable items for designing the DC-GIS is the effect of the particle contamination to electrical properties more crucial than conventional GIS. the particles floating around the high voltage conductor with negative DC voltage give the most detrimental effect to the insulation properties at application of positive lightning impulse. Therefore it is essential to study and elucidate the phenomena for the realization of compact and highly reliable DC-GIS.

A DC500kV transmission system will be operated at the beginning of the 21st century in Japan, and DC GIS will be used in this system. As DC500kV GIS is the first application of its type in the world, many insulation problems had to be solved.

The Kii-Channel HVDC link under construction in Japan is equipped with metallic return transfer breakers (MRTBs) in one converter station. A new MRTB for an interrupting current of 3500 A dc was developed. To interrupt a dc current, a method that produces a current zero point by superimposing a self-excited oscillatory current on a dc arc current was employed. For this purpose, an LC circuit was coupled in parallel to an SF6 gas circuit breaker. Developing an SF6 gas circuit breaker that has a large arc voltage drop gradient against currents permitted a large oscillatory current to be generated. A modified Mayr-type dynamic arc equation was newly presented. The dc interruption limits calculated using this equation agreed with the measured values.