Search

The 1/f spectra that appear in electroencephalogram data are among the characteristics that appear in the wide range of self-organizing phenomena encompassing both physical and sociological phenomena. The fact that they appear across the various objects suggests that the underlying cause of the 1/f spectra can be elucidated by using a simplified model that does not depend on the detailed structure of the objects. This paper, treating the electroencephalogram as a macro-quantity of neuron activities, demonstrates the existence of a self-similar solution through the spatial-temporal coarse-graining of a neural network, which is a simplified model of the brain. The self-similar solution in fact leads to the derivation of a 1/f spectrum. © 2003 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 87(1): 72–81, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.10016 [ABSTRACT FROM AUTHOR]

In the high-temperature process of semiconductors, the temperature distribution on the wafer surface during the procedures of the wafer insertion into the removal from the oxidation or diffusion furnace is important in determining the density of the dislocation due to the thermal stress and the uniformities of both the oxide thickness and the diffusion depth. As the size of a wafer and the density of integration increase, the analysis of the thermal transient characteristics becomes more important. This paper analyzes the model of the temperature transient characteristics proposed previously and describes the transient characteristics on a wafer by measuring the temperature distribution on a wafer in a furnace using an infrared radiometer. The simulation for a case where a wafer of 150 mm in diameter is inserted into furnace at a speed of 20 cm/min indicates that the temperature variation on a wafer at every moment is as high as 150°C. This result agrees with the experimental result within an accuracy of 25°C. When the insertion speed is 100 cm/min, the temperature variation increases by 20 to 30 percent and is maintained until the wafer reaches the high-temperature zone. This is caused by the increase in the rate of temperature change with time due to the radiation from the tube wall which is the external heat source. This tendency is more noticeable for wafers located at the middle row. [ABSTRACT FROM AUTHOR]

The nonuniform temperatures that develop over silicon wafers on insertion and removal from the furnaces used in the oxidation and diffusion processes of semiconductor fabrication are one factor in reduced yields. For example, because of temperature differences in the oxidation process there are thermal stresses and differing thermal hystereses over the wafer surface which degrade the uniformity of the oxide layer formed. The most pronounced temperature differences, occurring when the wafers are inserted into the furnace, develop mainly because of the effect of the boat μg which supports the wafers. Since the heat capacity of the boat is much greater than that of the wafers, during the slower rise in the boat temperature radiant heat exchange with the wafer bottoms keeps the temperature of the bottoms lower than the temperature of the wafer tops, which are almost unaffected by the boat. This transient in the wafer temperature depends on such process parameters as the boat insertion speed, the ratio between the wafer and furnace reactor tube diameters, and the wafer spacing. In order to analyze this temperature characteristic the process is modelled and the results of numerical simulation are compared with experiment. The model for the wafer temperatures inside the furnace is a system of coupled partial differential equations for the mostly radiant heat fluxes of the boat and wafers. With an insertion speed of 2 m/sec, both the experimental data and the model give a maximum temperature difference over the wafer surface of 230°C near the end of insertion, thus confirming the model. [ABSTRACT FROM AUTHOR]

In semiconductor fabrication it is difficult to form channels with precisely controlled lengths, even when using plasma etching which itself is highly precise. This is because of fluctuations in the processes preceding the etching, as, for example, in the developed resist dimensions. This paper proposes a method for controlling channel lengths which relies on an optimized over-etching, the extra etching time after the normal etch completion depending on the variation in resist dimension, etc. In the method a phenomenological model is set up for the rate of change of channel length as a function of the resist dimension and etching cross section, and the polysilicon layer thickness and Its phosphorus doping density as determined by sheet resistance. The model coefficients are estimated by a Kalman filter on wafer and lot measurement data. The results of production line experiments with the present method show a reduction in channel length variation by one-half compared with the previous uncontrolled method. [ABSTRACT FROM AUTHOR]

A systematic way for deriving the parameter renormalization group equation for one-dimensional maps is presented and the critical behavior of periodic doubling is investigated. Introducing a formal potential function in one-parameter cases, it is shown that accumulation points correspond to local potential maxima and universal constants are easily determined. The estimates of accumulation points and universal constants match the known values asymptotically when the order of potential grows large. The potential function shows scaling in the parameter space with the universal convergent rate at the accumulation point similar to the Feigenbaum universal function. For two-parameter cases, a parameter reduction transformation is found to be useful to determine some important fixed points. A locally defined potential function is introduced and its scaling property is discussed. (c) 1997 American Institute of Physics.