116 results on '"Mattausch, Hans Jurgen"'
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2. Model Development for Robust Design of SOI-MOSFET Circuits used in Radiative Environments
3. Simulation-Based Power-Loss Optimization of General-Purpose High-Voltage SiC MOSFET Circuit Under High-Frequency Operation
4. A carrier-transit-delay-based nonquasi-static MOSFET model for circuit simulation and its application to harmonic distortion analysis
5. Completely surface-potential-based compact model of the fully depleted SOI-MOSFET including short-channel effects
6. HiSIM2: Advanced MOSFET model valid for RF circuit simulation
7. Predictive Compact Modeling of Abnormal LDMOS Characteristics Due to Overlap-Length Modification
8. Universal Feature of Trap-Density Increase in Aged MOSFET and Its Compact Modeling
9. Modeling of Short-Channel Effect on Multi-Gate MOSFETs for Circuit Simulation
10. History Effect on Circuit Performance of SOI-MOSFETs
11. Force-Sensor-Based Surface Recognition With Surface-Property-Dependent Walking-Speed Adjustment of Humanoid Robot
12. Energy Efficiency of Force-Sensor-Controlled Humanoid-Robot Walking on Indoor Surfaces
13. Analysis of Sensor-Based Real-Time Balancing of Humanoid Robots on Inclined Surfaces
14. Electrical/thermal properties of nonplanar polyoxides and the consequent effects for EEPROM cell operation
15. NVDL-Cache: Narrow-Width Value Aware Variable Delay Low-Power Data Cache
16. Dynamic Pattern-Recognition-Based Walking-Speed Adjustment for Stable Biped-Robot Movement under Changing Surface Conditions
17. Status and trends of power semiconductor device models for circuit simulation
18. Modeling of Temperature-Dependent MOSFET Aging
19. Power Reduction and BTI Mitigation of Data-Cache Memory Based on the Storage Management of Narrow-Width Values
20. Compact Modeling for Leading-Edge Thin-Layer MOSFETs with Additional Applicability in Device optimization toward Suppressed Short-Channel Effects
21. Analysis of IGBT Charging/Discharging Mechanism for Accurate Compact Modeling
22. Validation on Duality in Impact-ionization Carrier Generation at the Onset of Snapback in Power MOSFETs
23. A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier
24. Leading-Edge Thin-Layer MOSFET Potential Modeling Toward Short-Channel Effect Suppression and Device Optimization
25. Potential-Based Modeling of Depletion-Mode MOSFET Applicable for Structural Variations
26. A Modular and Reconfigurable Pipeline Architecture for Learning Vector Quantization
27. A Hardware Architecture for Cell-Based Feature-Extraction and Classification Using Dual-Feature Space
28. Consistent Modeling of Snapback Phenomenon Based on Conventional I-V Measurements
29. Modeling of Carrier Trapping and Its Impact on Switching Performance
30. Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS
31. Consistent Predictive Simulation of SRAM-Cell Performance Degradation Including Both MOSFET Fabrication Variation and Aging
32. Circuit-aging modeling based on dynamic MOSFET degradation and its verification
33. Aging simulation of SiC-MOSFET in DC-AC converter
34. Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction
35. A Memory-Based Modular Architecture for SOM and LVQ with Dynamic Configuration
36. K-Nearest Neighbor Associative Memory with Reconfigurable Word-Parallel Architecture
37. Analysis of GaN-HEMTs switching characteristics for power applications with compact model including parasitic contributions
38. Dynamically reconfigurable system for LVQ-based on-chip learning and recognition
39. Word-parallel associative memory for k-nearest-neighbor with configurable storage space of reference vectors
40. Compact modeling and analysis of the Partially-Narrow-Mesa IGBT featuring low on-resistance and low switching loss
41. Compact Modeling of the Transient Carrier Trap/Detrap Characteristics in Polysilicon TFTs
42. A SoPC architecture for nearest-neighbor based learning and recognition
43. LVQ neural network SoC adaptable to different on-chip learning and recognition applications
44. The HiSIM compact models of high-voltage/power semiconductor devices for circuit simulation
45. A coprocessor for clock-mapping-based nearest Euclidean distance search with feature vector dimension adaptability
46. Universal NBTI Compact Model for Circuit Aging Simulation under Any Stress Conditions
47. Compact Modeling of SOI MOSFETs With Ultrathin Silicon and BOX Layers
48. A Hardware-Accelerated Reduced Dimensionality Multi-Prototype Learning and Recognition System with complementary classifiers
49. Word-parallel coprocessor architecture for digital nearest Euclidean distance search
50. Modeling of injection enhanced IGBT for accurate of switching performance
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