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In this work, we report an experimental investigation of pulsed laser deposition (PLD) of thin Gd:HfO2 layers at 330 °C, which show ferroelectric behavior after annealing at 450 °C, compatible with...

This experimental study investigates a novel multi-functional one dimensional-two dimensional (1D-2D) heterojunction made of two different band-gap semiconductors, i.e. single-walled carbon nanotube (SWCNT) and tungsten di-selenide (WSe2). The proposed ultra-scaled van der Waals junction behaves like a ${p}$ -type field-effect transistor (FET) or a gated ${p}$ - ${n}$ diode, depending upon the gate bias. A detailed physical study of charge transportation mechanism is presented in a wide range of applied potentials. The obtained results are important towards scaling nanoelectronics to atomic thicknesses by means of the 1D-2D hybrid junctions with additional multi-functional solid-state devices.

We report the fabrication process and performance characterization of a fully integrated ferroelectric gate stack in a WSe2/SnSe2 Tunnel FETs (TFETs). The energy behavior of the gate stack during charging and discharging, together with the energy loss of a switching cycle and gate energy efficiency factor are experimentally extracted over a broad range of temperatures, from cryogenic temperature (77 K) up to 100 °C. The obtained results confirm that the linear polarizability is maintained over all the investigated range of temperature, being inversely proportional to the temperature T of the ferroelectric stack. We show that a lower-hysteresis behavior is a sine-qua-non condition for an improved energy efficiency, suggesting the high interest in a true NC operation regime. A pulsed measurement technique shows the possibility to achieve a hysteresis-free negative capacitance (NC) effect on ferroelectric 2D/2D TFETs. This enables sub-15 mV dec−1 point subthreshold slope, 20 mV dec−1 average swing over two decades of current, ION of the order of 100 nA µm−2 and ION/IOFF > 104 at Vd = 1 V. Moreover, an average swing smaller than 10 mV dec−1 over 1.5 decades of current is also obtained in a NC TFET with a hysteresis of 1 V. An analog current efficiency factor, up to 50 and 100 V−1, is achieved in hysteresis-free NC-TFETs. The reported results highlight that operating a ferroelectric gate stack steep slope switch in the NC may allow combined switching energy efficiency and low energy loss, in the hysteresis-free regime.

We propose double-gated n-type WSe2 FETs with low leakage, low hysteresis top gate high-k dielectric stack. The top gate dielectric layer is deposited by HfO2 ALD on an Al2O3 seed layer obtained from the evaporation and oxidation by air exposure of a 1.5 nm Al layer. When operated under back gate control, the fabricated WSe2 FETs behave as n-type enhancement transistors with ON/OFF current ratios exceeding 6 orders of magnitude and a ON current close to 1 μA/μm at a drain bias of 100 mV. An applied negative top gate bias determines a much steeper turn-on of the back gated transfer characteristic and a reduction of the observed hysteresis. Top gate devices behave as n-type depletion FETs, reaching a ION/IOFF ratio larger than 106 under positive bias applied to the back gate. The electron mobility, extracted using the Y-function method, was estimated to be 22.15 cm2V-1s-1 under a drain bias of 1 mV. We characterize the hysteresis dynamics in our devices, demonstrating a substantial improvement with respect to comparable top gated MoS2 FETs.

In this letter we report and investigate the temperature dependency of various radio frequency parameters (RF) for a fabricated reconfigurable bandstop filter with vanadium dioxide (VO2) switches measured up to 55 GHz. Here the insulator to metal (ITM) and metal to insulator transition (MIT) hysteresis of the VO2 thin film influence on the RF characteristics of the filters is analyzed from 25 {\deg}C and 120 {\deg}C in heating and cooling. The resonance frequency and maximum insertion loss (IL) stability and sensitivity with temperature variations are explored. It is noticed that increasing the temperature with 50 {\deg}C from 25 {\deg}C (or decreasing it with 50 {\deg}C from 120 {\deg}C) will result in a less than 1% fractional frequency shift in respect to the off and on resonance frequencies. The sharp DC conductivity levels variations of the VO2 thin film around the transition temperatures translate into sharp effects on the resonance characteristics of the filters. On the contrary, the maximum IL levels are less sensitive to the DC films sharp conductivity changes around the VO2 transition temperature. Last, we see that the RF parameters in heating and cooling at 80 {\deg}C, above (but close to) the DC transition temperatures of VO2 exhibit completely different resonance frequencies. The RF results reported close to the transition temperatures for the VO2 thin films can diverge in heating and cooling, thus of a more insightful understanding of VO2 reconfigurable RF devices has to include temperature dependent measurements at various temperatures below MIT and ITM in the RF ranges too, Comment: 14 pages, 7 figs. This article is under submission at Applied Physics Letters

Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by using quantum mechanical band-to-band tunneling and excellent electrostatic control. Meanwhile, negative capacitance (NC) of ferroelectrics has been proposed as a promising performance booster of MOSFETs to bypass the aforementioned fundamental limit by exploiting the differential amplification of the gate voltage under certain conditions. We combine these two principles into a single structure, a negative capacitance heterostructure TFET, and experimentally demonstrate a double beneficial effect: (i) a super-steep SS value down to 10 mV/decade and an extended low slope region that is due to the NC effect and, (ii) a remarkable off-current reduction that is experimentally observed and explained for the first time by the effect of the ferroelectric dipoles, which set the surface potential in a slightly negative value and further blocks the source tunneling current in the off-state. State-of-the-art InAs/InGaAsSb/GaSb nanowire TFETs are employed as the baseline transistor and PZT and silicon-doped HfO2 as ferroelectric materials.

Two-dimensional/two-dimensional (2D/2D) heterojunctions form one of the most versatile technological solutions for building tunneling field effect transistors because of the sharp and potentially clean interfaces resulting from van der Waals assembly. Several evidences of room temperature band-to-band tunneling (BTBT) have been recently reported, but only few tunneling devices have been proven to break the Boltzmann limit of the minimum subthreshold slope, 60 mV per decade at 300 K. Here, we report the fabrication and characterization of a vertical p-type Tunnel FET (TFET) co-integrated on the same flake with a p-type MOSFET in a WSe2/SnSe2 material system platform. Due to the selected beneficial band alignment and to a van der Waals device architecture having an excellent heterostructure 2D–2D interface, the reported tunneling devices have a sub-thermionic point swing, reaching a value of 35 mV per decade, while maintaining excellent ON/OFF current ratio in excess of 105 at VDS = 500 mV. The TFET characteristics are directly compared with the ones of a WSe2 MOSFET realized on the very same flake used in the heterojunction. The tunneling device clearly outperforms the 2D MOSFET in the subthreshold region, crossing its characteristic over several orders of magnitude of the output current and providing better digital and analog figures of merit.

In this work we report the fabrication, co-integration and resulting performance of 2D/2D van der Waals (vdW) Vertical p-type Tunnel FETs and p-MOSFETs in a WSe 2 /SnSe 2 material system. We demonstrate the best ever reported combined performance in terms of subthermionic subthreshold swing (point swing less than 35 mV/dec and average swing smaller than 50 mV/dec over 1.5 decade at V DS from 300 mV to 700mV), I OFF ON ~10 nA/um2 and I ON /I OFF > 105 at V DS = 500 mV, for a 2D/2D vertical Tunnel FET. Moreover, for the first time, the fabricated Tunnel FET shows clear regions of higher performance, in same 2D material system, than the 2D MOSFET below 500 mV. NDR at room temperature in the output characteristic, with I peak /I valley >10, demonstrates the dominant BTBT conduction. The low hysteresis of the devices show high quality HfO 2 gating with defect-free vdW gaps between the flakes.Finally, for the first time, we co-integrate on a single WSe 2 flake, using 4-terminal design and a common gate, a pTunnel FET and a pMOSFET with different threshold voltages. These can operate in parallel as Dual-Transport Switch: this device shows subthermionic swing (~55mV/dec point swing) of the TFET and a thermionic high on-current (~100nA/um2 at V DS = 500mV) summing-up MOSFET and Tunnel FET currents, outperforming the individual components.

The new class of fully silicon-compatible hafnia-based ferroelectrics with high switchable polarization and good endurance and thickness scalability shows a strong promise for new generations of logic and memory devices. Among other factors, their competitiveness depends on the power efficiency that requires reliable low-voltage operation. Here, we show genuine ferroelectric switching in HfxZr(1–x)O2 (HZO) layers in the application-relevant capacitor geometry, for driving signals as low as 800 mV and coercive voltage below 500 mV. Enhanced piezoresponse force microscopy with sub-picometer sensitivity allowed for probing individual polarization domains under the top electrode and performing a detailed analysis of hysteretic switching. The authentic local piezoelectric loops and domain wall movement under bias attest to the true ferroelectric nature of the detected nanodomains. The systematic analysis of local piezoresponse loop arrays reveals a totally unexpected thickness dependence of the coercive fields...

In this paper, we experimentally explore the transient negative capacitance effect in ferroelectric high-k gate stacks using multi-ferroelectric domain Si-doped HfO 2 with and without the metal plane, MFMIS (TiN/Si:HfO 2 /TiN/SiO 2 ) and MFIS (TiN/Si:HfO 2 /SiO 2 ) respectively. With optimized 500ns pulsed measurements, we compare the reconstructed transient S-shaped P-E curves of the two gate stacks using ~100nm ferroelectric multi-domains and distinguish the non-switching hysteresis-free NC effect from unstable FE switching hysteretic phenomena. We experimentally validate that the use of a metal layer in between the ferroelectric and the dielectric can inherently destabilize NC due to domain formation. Furthermore, from P-E of both ferroelectric stacks using 10nm Si-doped HfO 2 , we extract the negative values of C FE and prove that the metal plane provides 60% higher values of the negative capacitance for MFMIS resulting in unstable hysteretic NC FET behavior. In contrast, the MFIS gate stack benefits from independent domain operation and achieves large and stable NC regions. We demonstrate that despite the smaller gain (amplification) of surface potential, the MFIS structure provides hysteresis-free stable performance boosting in all the regimes of operation of a 14nm UTB SOI MOSFET and can be recommended as performance booster advanced NC FETs.

HfO2-based ferroelectrics are considered a promising class of materials for logic and memory applications due to their CMOS compatibility and ferroelectric figures of merit. A steep-slope field-effect-transistor (FET) switch is a device for logic applications in which a ferroelectric gate stack exploits a stabilized negative capacitance regime capable to differentially amplify the surface potential in a metal–oxide–semiconductor FET structure, resulting in the improvement of the subthreshold swing and overdrive. In a number of relevant studies of negative capacitance, intrinsic (thermodynamic) switching is assumed, since alternative switching scenarios predict undesirable hysteretic responses in logic devices. However, there is little support from the experimental data showing that the polarization reversal in HfO2-based ferroelectrics is really driven by the intrinsic switching mechanism. In this work, polarization hysteresis loops are measured over wide temperature ranges on polycrystalline Si-doped HfO2 (Si:HfO2) capacitors. The analysis herein, which is based on the classic Landau–Ginzburg–Devonshire theory, yields the temperature-dependent dielectric susceptibility values, which fit the Curie–Weiss law. The extrapolated Curie temperature value is in line with the data obtained for other HfO2-based ferroelectrics using different techniques. The work also illustrates a method to evaluate the ferroelectric equivalent negative capacitance value and range of voltages, aiming at study and optimization of a stabilized negative capacitance FET. This study indicates that the intrinsic switching provides an adequate description of the polarization hysteresis in Si:HfO2 films. This confirms the usability of hafnia-based ferroelectrics for negative capacitance logic devices, and the important role that the intrinsic mechanism plays in the dielectric response of these materials.

The new class of fully silicon-compatible hafnia-based ferroelectrics with high switchable polarization and good endurance and thickness scalability shows a strong promise for new generations of logic and memory devices. Among other factors, their competitiveness depends on the power efficiency that requires reliable low-voltage operation. Here, we show genuine ferroelectric switching in Hf

This paper presents the design, fabrication, and electrical characterization of a reconfigurable RF capacitive shunt switch that exploits the electro-thermally triggered vanadium dioxide (VO2) insulator to metal phase transition. The RF switch is further exploited to build wide-band RF true-time delay tunable phase shifters. By triggering the VO2 switch insulator to metal transition (IMT), the total capacitance can be reconfigured from the series of two metal-insulator-metal (MIM) capacitors to a single MIM capacitor. The effect of bias voltage on losses and phase shift is investigated, explained, and compared to the state of the art in the field. We report thermal actuation of the devices by heating the devices above VO2 IMT temperature. By cascading multiple stages a maximum of 40° per dB loss close to 7 GHz were obtained.

ACS applied electronic materials 2(5), 1263-1272 (2020). doi:10.1021/acsaelm.0c00078, Published by ACS Publications, Washington, DC

This letter introduces a reconfigurable planar square-coil-shaped inductor exploiting as the tuning mechanism the insulator-to-metal transition (IMT) of a vanadium dioxide (VO2) switch placed in the interwinding space in an unprecedented manner. The VO2 thin-film bar-shaped switch is electrically connected to provide a temperature-selective current path that effectively short-circuits a part of the inductor coil changing the inductance of the device. The inductor is fabricated on a high-resistivity silicon substrate using a CMOS-compatible 2-D planar low-cost technology (four photolithography steps). The design, optimized to work in the 4-10-GHz range, provides measured inductances at 5 GHz of 2.1 nH at 20°C and 1.35 nH at 100°C with good stability in the entire frequency band (4-10 GHz) resulting in a reconfiguration ratio of 55%. The quality factor (Q-factor) at 7 GHz is about 8 at 20°C (off state) and 3 at 100°C (on state), outperforming tunable inductors employing VO2 with 2 orders of magnitude higher Q-factor and a smaller footprint. This represents an advancement for the state of the art of 2-D CMOS-compatible inductors in the considered frequency range.

Recently, the field of Metal-Insulator-Transition (MIT) materials has emerged as an unconventional solution for novel energy efficient electronic functions, such as steep slope subthermionic switches, neuromorphic hardware, reconfigurable radiofrequency functions, new types of sensors, terahertz and optoelectronic devices. Employing radiofrequency (RF) electronic circuits with a MIT material like vanadium Dioxide, VO2, requires appropriate characterization tools and fabrication processes. In this work, we develop and use 3D Smith charts for devices and circuits having complex frequency dependences, like the ones resulting using MIT materials. The novel foundation of a 3D Smith chart involves here the geometrical fundamental notions of oriented curvature and variable homothety in order to clarify first theoretical inconsistencies in Foster and Non Foster circuits, where the driving point impedances exhibit mixed clockwise and counter-clockwise frequency dependent (oriented) paths on the Smith chart as frequency increases. We show here the unique visualization capability of a 3D Smith chart, which allows to quantify orientation over variable frequency. The new 3D Smith chart is applied as a joint complex-scalar 3D multi-parameter modelling and characterization environment for reconfigurable RF design exploiting Metal-Insulator-Transition (MIT) materials. We report fabricated inductors with record quality factors using VO2 phase transition to program multiple tuning states, operating in the range 4 GHz to 10 GHz.

We propose and experimentally demonstrate double-gated n-type WSe2 FETs with excellent top gate high-k dielectric layer. Under back gate control, the devices behave as n-type enhancement transistors, with ON/OFF current ratios larger than 6 orders of magnitude and a ON current close to $1\ \mathbf{pA}/\mu\mathbf{m}$ under a drain bias of 100 mV. Negative top gate biases determine a much steeper turn-on of the back gated transfer characteristic and a reduction of the hysteresis. Top gated device behaves as n-type depletion FETs, exhibiting a $I_{\mathbf{ON}}/I_{\mathbf{OFF}}$ ratio larger than 106 under positive bias applied to the back gate. A minimum hysteresis of 40 mV and an average subthreshold slope close to 100 mV/dec prove the high quality of the deposited top gate dielectric. The electron mobility has been extracted using the Y-function method, obtaining 22.15 cm2V−1s−1 under a drain bias of 1 mV.

HfO2-based ferroelectrics have dramatically changed the application perspectives of polarization-switching materials for information processing and storage. Their CMOS compatibility and preservation of high reversible polarization down to a few nanometer thickness make them attractive for various device concepts including non-volatile memories and negative-capacitance-enhanced steep-slope transistors. In the context of these applications, the long-standing discussion of intrinsic (thermodynamic) or extrinsic nuclei-limited switching (NLS) in ferroelectrics has recently gained importance. In particular, the negative capacitance effect that is formally described by the Landau–Ginzburg–Devonshire formalism implies the intrinsic polarization switching driven by the thermodynamic coercive field. On the other hand, recent studies reported the nucleation-limited extrinsic switching, which does not result in the hysteresis-free negative capacitance effect. Here, we analyze the polarization response in the nanometer scale on the ferroelectric/dielectric bilayer where the negative capacitance has been previously demonstrated. Our analysis of the two limiting cases of quasi-static switching and the earlier reported ultra-fast polarization response supports the intrinsic polarization reversal scenario. The compatibility of this mechanism with the previously reported NLS region-by-region switching with remarkably low domain wall velocity is addressed. Our results confirm the usability of CMOS-compatible polycrystalline HZO ferroelectric films for gates operating in the negative-capacitance regime. Furthermore, they point towards possible solutions for optimizing their switching properties for applications including memories.