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A monitoring was conducted in 35 commercial vineyards located in Piedmont (North-West Italy) in September 2018 to test the sensitivity of Botrytis cinerea populations to the fungicides that were commonly used in the past and at present: benzimidazoles, dicarboximides, anilinopyrimidines, phenylpyrroles, hydroxyanilides and SDHI fungicides. Sensitivity was tested by evaluating the spore germination on a medium amended with a discriminatory concentration of the different tested botryticides. Conidial suspensions were prepared from infected, randomly sampled bunches and used for the tests. In comparison with the years 2008–2014, the following trend was recorded: benzimidazole resistance was quite stable and was found in about 50% of the vineyards involved in the monitoring; dicarboximide resistance had disappeared in the tested samples, while the frequency of resistance to anilinopyrimidines had increased; the resistance to fenhexamid had decreased; in the case of boscalid, the presence of resistance was quite stable; no resistance to phenylpyrroles was found, although the high discriminatory dose used for fludioxonil cannot exclude the presence in the tested vineyards of low levels of resistance to this fungicide, typical of multidrug-resistant strains.

The reduction of antimicrobial treatments and mainly the application of environmentally friendly compounds, such as resistance elicitors, is an impelling challenge to undertake more sustainable agriculture. We performed this research to study the effectiveness of non-conventional compounds in reducing leaf fungal attack and to investigate whether they influence the grape phyllosphere. Pathogenicity tests were conducted on potted Vitis vinifera &ldquo, Nebbiolo&rdquo, and &ldquo, Moscato&rdquo, cultivars infected with the powdery mildew agent (Erysiphe necator) and treated with three elicitors. Differences in the foliar microbial community were then evaluated by community-level physiological profiling by using BiologTM EcoPlates, high throughput sequencing of the Internal Transcribed Spacer (ITS) region, and RNA sequencing for the viral community. In both cultivars, all products were effective as they significantly reduced pathogen development. EcoPlate analysis and ITS sequencing showed that the microbial communities were not influenced by the alternative compound application, confirming their specific activity as plant defense elicitors. Nevertheless, &ldquo, plants were less susceptible to the disease and presented different phyllosphere composition, resulting in a richer viral community, when compared with the &ldquo, plants. The observed effect on microbial communities pointed to the existence of distinct genotype-specific defense mechanisms independently of the elicitor application.

Erysiphe necator is favourably influenced by the increase in temperatures and remains the main pathogen threatening grape in Northern Italy. In the present work, the efficacy of laminarin and calcium oxide in the control of grape powdery mildew was evaluated, comparing them to sulphur. Two tests were carried out on potted grape “Moscato” plants in 2017, and two field trials were carried out in Italy during 2016 and 2017 on a vineyard of the “Moscato” variety. Laminarin and calcium oxide showed, for the first time, to significantly reduce powdery mildew, and this occurred in all trials. However, laminarin was less effective than sulphur in potted trials and in 2016 field trial, and both laminarin and calcium oxide were less effective than sulphur in 2017 field trial.

The recent outbreak of bacterial canker on kiwifruit, caused by Pseudomonas syringae pv. actinidiae, has caused considerable damage to the international kiwifruit industry. Commercial products, and products under development, were evaluated over 2 years to assess their ability to control bacterial canker on kiwifruit under controlled conditions. The results were compared with two trials carried out in a kiwifruit orchard located in northern Italy during 2011 and 2012, to test the preventative efficacy of different copper formulations against P. syringae pv. actinidiae. In the greenhouse and orchard trials, copper hydroxide and the mixtures of copper hydroxide and copper oxychloride, significantly reduced the foliar symptoms by 70–80 % compared with the control, and showed low phytotoxicity. Similar efficacy was provided by acibenzolar-S-methyl, whose use has been temporarily extended to kiwifruit in Italy, with a maximum of four treatments per year. However, the product showed phytotoxicity on one-year old plants. The efficacy of fosetyl-Al was lower, particularly in the first orchard trials of 2012 and 2013. The efficacy of the other products tested never exceeded 30–40 %, and some products were not significantly different from the control. Kiwifruit plants grown in a steamed peat substrate mixed with compost obtained from digested organic matrices of municipal solid waste showed significantly fewer leaf spots compared with untreated controls. Copper compounds alternated with resistance inducers could be used in combination with compost, in order to develop new integrated control strategies to reduce the disease development and spread.

This investigation was undertaken to test different control strategies against Botrytis cinerea vineyards. Two commercial vineyards, "Barbera" and "Moscato," located in Piedmont (Northern Italy) were divided into seven plots and treated with different combinations of fungicides including fenhexamid, pyrimethanil, fludioxonil + cyprodinil, iprodione, and boscalid, a new carboxamide compound. An integrated strategy including a chemical (pyrimethanil) and a biocontrol agent (Trichoderma spp. t2/4ph1) was also included. At harvest, the percentage of bunches and berries attacked by B. cinerea and the concentration of the chemical fungicides were determined. All the pesticide residues at harvest were below the maximum residue level (MRL), except when two applications of pyrimethanil per season were applied. Boscalid was the most effective active ingredient against B. cinerea among the tested chemicals. When boscalid application was followed by a treatment with pyrimethanil, its efficacy was similar to that shown by two treatments of pyrimethanil. However, this second strategy was not feasible due to the risks of resistance development in the pathogen and to the residue accumulation as indicated by the analysis.

While modern processors offer a wide spectrum of software-controlled power modes, most datacenters only rely on dynamic voltage and frequency scaling (DVFS, a.k.a. P-states) to achieve energy efficiency. This paper argues that, in the case of datacenter workloads, DVFS is not the only option for processor power management. We make the case for per-core power gating (PCPG) as an additional power management knob for multi-core processors. PCPG is the ability to cut the voltage supply to selected cores, thus reducing to almost zero the leakage power for the gated cores. Using a testbed based on a commercial 4-core chip and a set of real-world application traces from enterprise environments, we have evaluated the potential of PCPG. We show that PCPG can significantly reduce a processor's energy consumption (up to 40%) without significant performance overheads. When compared to DVFS, PCPG is highly effective saving up to 30% more energy than DVFS. When DVFS and PCPG operate together they can save up to almost 60%.

Simulation has historically been the primary technique used for evaluating the performance of new proposals in computer architecture. Speed and complexity considerations have traditionally limited its applicability to single-thread processors running application-level code. This is no longer sufficient to model modern multicore systems running the complex workloads of commercial interest today. COTSon is a simulator framework jointly developed by HP Labs and AMD. The goal of COTSon is to provide fast and accurate evaluation of current and future computing systems, covering the full software stack and complete hardware models. It targets cluster-level systems composed of hundreds of commodity multicore nodes and their associated devices connected through a standard communication network. COTSon adopts a functional-directed philosophy, where fast functional emulators and timing models cooperate to improve the simulation accuracy at a speed sufficient to simulate the full stack of applications, middleware and OSs. This paper describes the changes in simulation philosophy we embraced in COTSon to address these new challenges. We base functional emulation on established, fast and validated tools that support commodity OSs and complex multitier applications. Through a robust interface between the functional and timing domain, we can leverage other existing simulators for individual sub-components, such as disks or networks. We abandon the idea of "always-on" cycle-based simulation in favor of statistical sampling approaches that can trade accuracy for speed. COTSon opens up a new dimension in the speed/accuracy space, allowing simulation of a cluster of nodes several orders of magnitude faster with a minimal accuracy loss.

In this paper we introduce CACTI-D, a significant enhancement of CACTI 5.0. CACTI-D adds support for modeling of commodity DRAM technology and support for main memory DRAM chip organization. CACTI-D enables modeling of the complete memory hierarchy with consistent models all the way from SRAM based L1 caches through main memory DRAMs on DIMMs. We illustrate the potential applicability of CACTI-D in the design and analysis of future memory hierarchies by carrying out a last level cache study for a multicore multithreaded architecture at the 32nm technology node. In this study we use CACTI-D to model all components of the memory hierarchy including L1, L2, last level SRAM, logic process based DRAM or commodity DRAM L3 caches, and main memory DRAM chips. We carry out architectural simulation using benchmarks with large data sets and present results of their execution time, breakdown of power in the memory hierarchy, and system energy-delay product for the different system configurations. We find that commodity DRAM technology is most attractive for stacked last level caches, with significantly lower energy-delay products.

This paper explores optimization techniques of the synchronization mechanisms for MPSoCs based on complex interconnect (Network-on-Chip), targeted at future mobile systems. We suggest the architecture of the memory controller optimized to minimize synchronization overhead. The proposed solution is based on the idea of performing synchronization operations which require the continuous polling of a shared variable, thus featuring large contention (e.g. spin locks), locally in the memory. We introduce a HW module, which augments the memory controller, the Synchronization-operation Buffer (SB), which queues and manages the requests issued by the processors. Experimental validation has been carried out by using GRAPES, a cycle-accurate performance/power simulation platform. For an 8-processor target architecture, we show that the proposed solution achieves up to 40% performance improvement and 25% energy saving with respect to synchronization based on the caching of the synchronization variables and directory-based coherency protocol. Furthermore, we prove the scalability of the proposed approach when the number of processors increases.

The paper introduces a dynamic branch prediction scheme suitable for energy-aware Very Long Instruction Word (VLIW) processors. The proposed technique is based on a compiler hint mechanism to filter the accesses to the branch predictor blocks. We define a configurable hint instruction which anticipates some static information about the upcoming branch to reduce the hardware involved in the prediction, thus, the energy consumption. To analyze the effectiveness of the proposed low-power branch prediction scheme, we combined it with some well-known dynamic branch prediction techniques suitable for VLIW processors. The analyzed branch predictors are characterized by simple hardware implementations, matching the low-power characteristics of the target VLIW processors. Experimental results have been carried out on Lx, an industrial 4-issue VLIW architecture.

To study the influence of environmental conditions on sporulation of Plasmopara viticola lesions under vineyard's conditions, unsprayed vines were inspected every second or third day and the numbers of sporulating and nonsporulating lesions were counted in two North Italy vineyards in 2008 to 2010. Infected leaves were removed so that only fresh lesions were assessed at each field assessment. Sporulation was studied at two scales, across field assessments and across the seasonal population of lesions. Frequencies of sporulating lesions were positively correlated with the numbers of moist hours in the preceding dark period (i.e., the number of hours between 8:00 p.m. and 7:00 a.m. with relative humidity ≥80%, rainfall >0 mm, or wetness duration >30 min). In a receiver operating characteristic analysis, predicted sporulation based on the occurrence of ≥3 moist hours at night provided overall accuracy of 0.85. To study the time course of sporulation on lesions which were not washed by rainfall, numbers of sporangia produced per square millimeter of lesion were estimated on individual cohorts of lesions over the whole infectious period. The numbers of sporangia per square millimeter of lesion increased rapidly during the first 4 days after the beginning of sporulation and then tapered off prior to a halt; the time course of cumulative sporangia production by a lesion followed a monomolecular growth model (R2 = 0.97). The total number of sporangia produced by a square millimeter of lesion increased as the maximum temperature decreased and moist hours in the dark increased. To study the release pattern of the sporangia, spore samplers were placed near grapevines with sporulating lesions. Airborne sporangia were caught in 91.2% of the days over a wide range of weather conditions, including rainless periods. The results of this study provide quantitative information on production of P. viticola sporangia that may help refine epidemiological models used as decision aids in grape disease management programs.

This paper presents Ally, a server platform architecture that supports compute-intensive management services on multi-core processors. Ally introduces simple hardware mechanisms to sequester cores to run a separate software environment dedicated to management tasks, including packet processing software appliances (e.g. for Deep Packet Inspection, DPI) with efficient mechanisms to safely and transparently intercept network packets. Ally enables distributed deployment of compute-intensive management services throughout a data center. Importantly, it uniquely allows these services to be deployed independent of the arbitrary OSs and/or hyper visor that users may choose to run on the remaining cores, with hardware isolation preventing the host environment from tampering with the management environment. Experiments using full system emulation and a Linux-based prototype validate Ally functionality and demonstrate low overhead packet interception, e.g., using Ally to host the well-known Snort packet inspection software incurs less over-head than deploying Snort as a Xen virtual machine appliance, resulting in up to 2x improvement in throughput for some workloads.

The increasing device count and design complexity are posing significant challenges to post-silicon validation. Bug diagnosis is the most difficult step during post-silicon validation. Limited reproducibility and low testing speeds are common limitations in current testing techniques. Moreover, low observability defies full-speed testing approaches. Modern solutions like on-chip trace buffers alleviate these issues, but are unable to store long activity traces. As a consequence, the cost of post-Si validation now represents a large fraction of the total design cost. This work describes a hybrid post-Si approach to validate a modern load-store queue. We use an effective error detection mechanism and an expandable logging mechanism to observe the microarchitectural activity for long periods of time, at processor full-speed. Validation is performed by analyzing the log activity by means of a diagnosis algorithm. Correct memory ordering is checked to root the cause of errors.