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As the industry moves from node to node, lithographers have been pushed to use complex models to correct overlay errors and drive down model residuals. High order models are now used in combination with Correction per Exposure capabilities for critical layers on immersion scanners [1]. Mean overlay intrafield signatures are linked to the reticles (current and reference) and illuminations used, therefore the intrafield High Order Process Correction (iHOPC) model should be as stable as possible in terms of correction parameters. However, iHOPC data shows that the overlay parameters can drift over time and a Run to Run can follow these slow drifts. IHOPC R2R integration in production overlay correction flow is discussed in this paper: How corrections are generated from overlay measurement? What metrics are used to secure the model application? What results on production lots can be achieved? Then, a focus is made on the model variability. To operate properly, the R2R needs a high frequency variability as low as possible. Some factors like scanner lens aberration correction, metrology tool matching, measurement layouts, have been found to have an impact on lot-to-lot variability. These effects will be investigated in this paper to provide a conclusion on the usage of an iHOPC R2R for mean overlay intrafield signatures.

Advanced nodes require tighter and tighter overlay control to secure products yield. Market like automotive one are even more demanding on “overlay reliability” till the extreme edge of wafers. High order models including Correction per Exposure capabilities are now introduced on the most critical immersion layers to put extra correction on the edge of wafers scanner fields. To ensure a correction model able to bring back these fields under overlay specification, the understanding of key process/equipment parameters to be put under control is needed. In this paper, choices done in term of overlay and Run to Run model will be discussed. On tools aspects, scanner table clean frequency impact and etch chambers variability will be addressed. In addition, etch recipe can modulate this etch chamber effect. The paper will conclude on the compromise to face in order to better correct and control overlay at the Edge of Wafer with the current Litho/Etch tools capabilities and R2R model strategy, at an acceptable cost (tool efficiency) and effort (rework, R2R complexity, …)

I.IntroductionWith overlay requirements getting more and more critical, a lot of work has been done in the industry to improve the overlay correction capability by using high order process corrections, corrections per exposure and heating control (lens and reticle). Another part of the overlay budget is linked to our ability to control and stabilize it through time as well as being reactive to changes via the advanced process control system of the fab (APC)[1]. This paper describes the steps taken from an individual feedback loops configuration (one technology, one or several similar layers) to large perimeter overlay run- to-run for a high-mix 300mm semiconductor logic fab[2]. First, a multivariate APC system is defined with all the specificities needed to enable a large perimeter configuration. Then, technology/layer grouping is explained as well as filters and limits settings to start the new feedback loops simulation. The simulation phase or "learning mode" allows to have an overview on the expected gains: enhanced reactivity to parameters drift and easier maintenance by engineers in charge of following overlay run-to-run, which indirectly leads to better overall APC performance. After overlay large perimeter activation, the alert number drastically decreases, risk of measurement sampling is minimized in the fab and a similar approach is started on energy large perimeter (CD: Critical Dimensions).

On product wafers, scanner focus is better controlled at the wafer center than at the wafer edge. This is due, in a large part, to edge roll off effects [1]. This paper quantifies the impact of edge roll off on scanner levelling non-correctable errors and correlates this to on-product effects. The main contributors and mitigation methods are also discussed for a NXT:1950 scanner.

The understanding and control of the intra-field overlay budget becomes crucial particularly after the introduction of multi-patterning applications. The intra-field overlay budget is built-up out of many contributors, each with its own characteristic. Some of them are (semi-)static like the reticle writing error (RWE) fingerprint, the scanner lens fingerprint, or the intra-field processing signature. Others are more dynamic. Examples are reticle heating and lens heating due to the absorption of a small portion of the exposure light. Ideally, all overlay contributors that are understood and known could be taken out of the feed-back control loop and send as feed-forward corrections to the scanner. As a consequence, only non-correctable overlay residuals are measured on the wafer. In the current work, we have studied the possibility to characterize the reticle writing error fingerprint by an off-line position measurement tool and use this information to send feed-forward corrections to the ASML TWINSCAN TM exposure tool. The current work is an extension of the work we published earlier. To this end, we have selected a reticle pair out of 50 production reticles that are used to manufacture a 28-nm technology device. These two reticles are special in the sense that the delta fingerprint contains a significant higher order RWE signature. While previously only the linear parameters were sent as feed-forward corrections to the ASML TWINSCAN TM exposure tool, this time we additionally demonstrate the capability to correct for the non-linear terms as well. Since the concept heavily relies on the quality of the off-line mask registration measurements, a state-of-the-art reticle registration tool was chosen. Special care was taken to eliminate any effects of the tool induced shifts that may affect the quality of the measurements. The on-wafer overlay verification measurements were performed on an ASML YieldStar metrology tool as well as on a different vendor tool. In conclusion, we have extended and proven the concept of using off-line reticle registration measurements to enable higher order feed-forward corrections the ASML TWINSCAN TM scanner. This capability has been verified by on-wafer overlay measurements. It is demonstrated that the RWE contribution in the overlay budget can be taken out of the feedback control loop and sent as feed-forward corrections instead. This concept can easily be extended when more scanner corrections become available.

For C040 technology and below, photolithographic depth of focus control and dispersion improvement is essential to secure product functionality. Critical 193nm immersion layers present initial focus process windows close to machine control capability. For previous technologies, the standard scanner sensor (Level sensor - LS) was used to map wafer topology and expose the wafer at the right Focus. Such optical embedded metrology, based on light reflection, suffers from reading issues that cannot be neglected anymore. Metrology errors are correlated to inspected product area for which material types and densities change, and so optical properties are not constant. Various optical phenomena occur across the product field during wafer inspection and have an effect on the quality and position of the reflected light. This can result in incorrect heights being recorded and exposures possibly being done out of focus. Focus inaccuracy associated to aggressive process windows on critical layers will directly impact product realization and therefore functionality and yield. ASML has introduced an air gauge sensor to complement the optical level sensor and lead to optimal topology metrology. The use of this new sensor is managed by the AGILE (Air Gauge Improved process LEveling) application. This measurement with no optical dependency will correct for optical inaccuracy of level sensor, and so improve best focus dispersion across the product. Due to the fact that stack complexity is more and more important through process steps flow, optical perturbation of standard Level sensor metrology is increasing and is becoming maximum for metallization layers. For these reasons AGILE feature implementation was first considered for contact and all metal layers. Another key point is that standard metrology will be sensitive to layer and reticle/product density. The gain of Agile will be enhanced for multiple product contribution mask and for complex System on Chip. Into ST context (High mix logic Fab) in term of product and technology portfolio AGILE corrects for up to 120nm of product topography error on process layer with less than 50nm depth of focus Based on tool functionalities delivered by ASML and on high volume manufacturing requirement, AGILE integration is a real challenge. Regarding ST requirements “Automatic AGILE” functionality developed by ASML was not a turnkey solution and a dedicated functionality was needed. A “ST homemade AGILE integration” has been fully developed and implemented within ASML and ST constraints. This paper describes this integration in our Advanced Process Control platform (APC).

On-product overlay can be improved through the use of context data from the fab and the scanner. Continuous improvements in lithography and processing performance over the past years have resulted in consequent overlay performance improvement for critical layers. Identification of the remaining factors causing systematic disturbances and inefficiencies will further reduce overlay. By building a context database, mappings between context, fingerprints and alignment & overlay metrology can be learned through techniques from pattern recognition and data mining. We relate structure (‘patterns’) in the metrology data to relevant contextual factors. Once understood, these factors could be moved to the known effects (e.g. the presence of systematic fingerprints from reticle writing error or lens and reticle heating). Hence, we build up a knowledge base of known effects based on data. Outcomes from such an integral (‘holistic’) approach to lithography data analysis may be exploited in a model-based predictive overlay controller that combines feedback and feedforward control [1]. Hence, the available measurements from scanner, fab and metrology equipment are combined to reveal opportunities for further overlay improvement which would otherwise go unnoticed.

The on-product overlay specification and Advanced Process Control (APC) are getting extremely challenging particularly after the introduction of multi-patterning applications like Litho-Etch-Litho-Etch (LELE). While the Reticle Writing Error (RWE) contribution could be marginalized for quite some time in the layer-to-layer overlay budget, it will become one of the dominating overlay contributors when the intra-layer overlay budget is considered. While most of the overlay contributors like wafer processing, scanner status, reticle transmission, dose, illumination conditions drop out of the intra-layer overlay budget, this is certainly not the case for reticle to reticle writing differences. In this work, we have studied the impact of the RWE on the on-product overlay performance. We show that the RWE can be characterized by an off-line mask registration tool and the modelled results can be sent as feed-forward corrections to the ASML TWINSCANTM. By doing so, the overlay control complexity (e.g. send-ahead wafers, APC settling time) can be reduced significantly. Off-line characterization enables that all reticles virtually become equal after correction (at least to the level of correction capability of the scanner). This means that all higher order RWE contributions (currently up to a third order polynomial) can be removed from the fingerprint. We show that out of 50 production reticles (FEOL, 28-nm technology), 30% can be improved on residual level when non-linear feed-forward corrections are considered as well. The additional benefit of feeding forward linear corrections to the scanner is even higher: it is anticipated that a large portion of the APC variation might find its origin in the RWE contribution. In order to send feed-forward corrections to the scanner, we obviously rely on the quality of the off-line RWE measurements. These measurements are usually provided by a registration tool at the mask shop. To secure the quality, an independent experimental verification test was developed to check if off-line RWE measurements can be used as feed-forward corrections to the scanner. The test has been executed on an ASML NXT: 1950i scanner and was designed such to isolate the reticle writing error contribution. The match between the off-line measurements and the experiment is striking.

Advanced CMOS nodes require more and more information to get the wafer process well setup. Process tool intrinsic capabilities are not sufficient to secure specifications. APC systems (Advanced Process Control) are being developed in waferfab to manage process context information to automatically adjust and tune wafer processing. The APC manages today Run to Run component from and between various process steps plus a sub-recipes/profiles corrections management. This paper will outline the architecture of an integrated/holistic process control system for a high mix advanced logic waferfoundry.

The continuous need for lithography overlay performance improvement is a key point for advanced integrated circuit manufacturing. Overlay control is more and more challenging in the 2x nm process nodes regarding functionality margin of the chip and tool capability. Transistor architecture rules which are set, confirm poly to contact space as the most critical one for 28nm technology node. Critical Dimension variability of these layers, even with best in class process stability, in addition to design constraint lead to on product overlay specifications of around 7nm. In order to ensure that the target is met in production environment and to identify potential ways for improvement, identification of the contributors to overlay errors is essential. We have introduced a novel budget breakdown methodology using both bottom-up and top-down overlay data. For the bottom up part, we have performed extensive testing with very high sampling scheme so as to quantify the main effects. In-line overlay metrology data has been used for top down approach to verify the overall performance in production. In this paper we focused on the 28nm contact to gate overlay in a FDSOI process. The initial inconsistency between bottom up and top down results led us to further exploration of the root cause of these inconsistencies. We have been able to highlight key figures to focus on, like reticle heating, wafer table contamination and etch processing effects. Finally, we conclude on 7nm overlay target achievement feasibility in high volume manufacturing environment.

We introduced a very simple overlay feed forward correction based on lot data issued from previous lithography operations. Simple method for correction factor optimization was also proposed. We applied this method in various cases based on 28nm node early production: implants lithography on 248nm tools, contact holes double patterning on 193nm immersion tool, and we also tried to improve contact holes patterning based on 248nm lithography data. All analysis were based on early production 28nm node data mixing 28LP and 28FDSOI technologies. We first optimized the correction based on our simple approach, and then compute the dispersion of all linear overlay parameters. Maximum modeled overlay error was also computed. In most cases we obtained significant improvements. The interest of such a very simple approach that requires reduced software development and allows simple implementation was thus demonstrated.

We introduced a simple method based on scatterometry measurement performed on dense contact holes matrix to investigate intrafield focus deviation on 28nm FDSOI real production wafers at contact holes patterning lithography operation. A complex three-dimensional scatterometry model with all patterned resist geometrical parameters left as degree of freedom. Then simple linear relationships between patterned resist geometrical parameters on the one hand, and applied dose and focus offset on the other hand were used to determine a focus and dose decorrelation model. This model was then used to investigate the effect of ASML AGILETM scanner option on intrafield focus deviation. A significant 16% intrafield focus standard deviation improvement was found with AGILETM, which validated our method and shows the possibilities of AGILETM option for intrafield focus control. This focus investigation method may be used to improve advanced CMOS manufacturing process control.

In the last years a flourishing number of techniques such as High Order Control or mappers have been proposed to improve overlay control. However a sustainable improvement requires sometimes understanding the underlying causes of the overlay limiting factors in order to remove them when possible or at least to keep them under control. Root cause finding for overlay error is a tough task due the very high number of influencing parameters and the interaction of the usage conditions. This paper presents a breakdown methodology to deal with this complexity and to find the contributors of overlay error variation. We use a Partial Least Squares (PLS) algorithm to isolate the key contributors for correctable terms and a field-to-field linear regression technique to highlight the main causes of residuals. We present a study carried out on 45nm CMOS contact-gate overlay over 687 production wafers exposed in an ASML TWINSCAN XT:1700i Immersion scanner. We present the results of the correlations with the 180 process and equipment variables used for this study. For each isolated contributor we propose an explanation of the underlying physical phenomenon and solutions.

This paper present an evaluation of our CMOS 45nm gate patterning process performance based on immersion lithography in a production environment. A CD budget breakdown is shown detailing lot to lot, wafer to wafer, intrawafer, intrafield and proximity CD uniformity characterization. Emphasis is given on scatterometry library development and deployment. We also look more into detail to focus effect on CD control. Finally status of overlay performance with immersion lithography is also presented.

In this paper we performed an analysis of various data collection preformed on C045 production lots in order to assess the influence of STI oxide layers on the CD uniformity of implant photolithography layers. Our final purpose is to show whether the DOSE MAPPER TM software option for interfiled dose correction available on ASML scanners combined with a run-to-run feed-forward regulation loop could improve global CD uniformity on C045 implants layers. After a brief presentation of the C045 implants context the re sults of the analysis are pres ented : swing curves, process windows analysis, and intra-die CD measurements are presented. The conclusion of the analysis is that it is not possible, in the current C045 industrial environment, to use a robust and general method of interfield dose correction in order to achieve a better global CD uniformity. Keywords: Photolithography, STI, Implant, Process Control, Swing Curve, Feedback, Feed-Forward, Metrology, Optical CD, Mask, Interfield.

International audience; CMOS 65nm technology node requires the introduction of advanced materials for critical patterning operations. The study is focused on the multilayer Anti Reflective Coating (ARC) stack, used in photolithography, for the gate patterning such as Advanced Patterning Film (APF). The interest on this new and complex ARC stack lies in the benefit to guarantee low CD dispersion thanks to a better reflectivity control and resist budget which leads to a larger lithographic process window. However, it implies numerous metrology challenges. The paper deals with the challenges of monitoring the gate Critical Dimension (CD) on this stack. The validation of the scatterometry model versus stack thicknesses and indexes variations, through experiments, is also described. The final result is the complete characterization of the materials for thickness and scatterometry CD control, for photo feedback and for etch feed-forward deployment in an industrial mode. The analysis shows that scatterometry measurements on a standard 65 nm gate process ensure a better effectiveness than the CD Scanning Electron Microscopy (SEM) ones when injected in the Advanced Process Control (APC) system from photo to etch.

Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (>0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (