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Data deduplication is a crucial technique for packing data and reducing duplication when transferring data. It is widely used in the cloud to restrict the usage of capacity memory and aids in transmission capacity sparing. Before redistributing data, an encryption mechanism is used to ensure the integrity of sensitive data during the deduplication process. The SHA algorithm is being used to save data in text format. To generate the security bits, padding is appended to the text. In de-duplication, it calculates the hash, i.e. hexadecimal number, string, and integer data. Hash-based de-duplication is the implementation of whole file hashing to the entire file. Text data’s hash values are considered to as feature properties. In contrast to traditional deduplication solutions, clients that transfer data to the cloud certify duplication inside the cloud data. In virtualization, both limiting primary memory size and memory blockage are considered important bottlenecks. Memory deduplication identifies pages with the same content and merges them into a single data file, reducing memory usage, memory parceling, and improving execution. In cloud storage, the MPT is used to deduplication so that it is used in single copies of the same data for different data owners. If any data users try to replicate the same data, it will be mapped and related to the archive data, implying that the data can’t be stored away. To ensure cloud data security, encryption techniques are used to encrypt data throughout deduplication procedures and prior to outsourcing cloud data.

The University of California’s Project Genie was an ARPA sponsored project to create an interactive programming environment. The SDS-930 was a relatively inexpensive machine with a maximum of 32 K of physical memory. To create a time-sharing machine from the base SDS-930 architecture, Pirtle and Lichtenberger extended the ’930 architecture to include protection and memory mapping. Deutsch and Lampson implemented an operating system for the modified ’930. Ultimately, SDS decided to market the Berkeley modifications to the ’930 and denoted it the ’940. They sold the machine to a new company called Tymshare. Tymshare heavily modified the Berkeley operating system over more than five years. Utilizing the system call manuals and the source code from Tymshare, it is possible to trace the operating system modifications that parallel the development of disk and telecommunication hardware in the late 1960s and early 1970s. It also illustrates what is required to turn a prototype system into a hardened commercial success.

The analysis and processing of big data are one of the most important challenges that researchers are working on to find the best approaches to handle it with high performance, low cost and high accuracy. In this paper, a novel approach for big data processing and management was proposed that differed from the existing ones; the proposed method employs not only the memory space to reads and handle big data, it also uses space of memory-mapped extended from memory storage. From a methodological viewpoint, the novelty of this paper is the segmentation stage of big data using memory mapping and broadcasting all segments to a number of processors using a parallel message passing interface. From an application viewpoint, the paper presents a high-performance approach based on a homogenous network which works parallelly to encrypt-decrypt big data using AES algorithm. This approach can be done on Windows Operating System using .NET libraries.

Number theoretic transform (NTT) is widely utilized to speed up polynomial multiplication, which is the critical computation bottleneck in a lot of cryptographic algorithms like lattice-based post-quantum cryptography (PQC) and homomorphic encryption (HE). One of the tendency for NTT hardware architecture is to support diverse security parameters and meet resource constraints on different computing platforms. Thus flexibility and Area-Time Product (ATP) become two crucial metrics in NTT hardware design. The flexibility of NTT in terms of different vector sizes and moduli can be obtained directly. Whereas the varying strides in memory access of in-place NTT render the design for different radix and number of parallel butterfly units a tough problem. This paper proposes an efficient conflict-free memory mapping scheme that supports the configuration for both multiple parallel butterfly units and arbitrary radix of NTT. Compared to other approaches, this scheme owns broader applicability and facilitates the parallelization of non-radix-2 NTT hardware design. Based on this scheme, we propose a scalable radix-2 and radix-4 NTT multiplication architecture by algorithm-hardware co-design. A dedicated schedule method is leveraged to reduce the number of modular additions/subtractions and modular multiplications in radix-4 butterfly unit by 20% and 33%, respectively. To avoid the bit-reversed cost and save memory footprint in arbitrary radix NTT/INTT, we put forward a general method by rearranging the loop structure and reusing the twiddle factors. The hardware-level optimization is achieved by excavating the symmetric operators in radix-4 butterfly unit, which saves almost 50% hardware resources compared to a straightforward implementation. Through experimental results and theoretical analysis, we point out that the radix-4 NTT with the same number of parallel butterfly units outperforms the radix-2 NTT in terms of area-time performance in the interleaved memory system. This advantage is enlarged when increasing the number of parallel butterfly units. For example, when processing 1024 14-bit points NTT with 8 parallel butterfly units, the ATP of LUT/FF/DSP/BRAM n radix-4 NTT core is approximately 2.2 × /1.2 × /1.1 × /1.9 × less than that of the radix-2 NTT core on a similar FPGA platform.

Three-dimensional network-on-chip (NoC) is the primary interconnection method for 3D-stacked multicore processors due to their excellent scalability and interconnect flexibility. With the support of 3D NoC, 3D non-uniform cache architecture (NUCA) is commonly used to organize the last-level cache (LLC) due to its high capacity and fast access latency. However, owing to the layered structure that leads to longer heat dissipation paths and variable inter-layer cooling efficiency, 3D NoC experiences a severe thermal problem that has a big impact on the reliability and performance of the chip. In traditional memory-to-LLC mapping in 3D NUCA, the traffic load in each node is inconsistent with its heat dissipation capability, causing thermal hotspots. To solve the above problem, we propose a temperature-balanced NUCA mapping mechanism named TB-NUCA. First, the Bayesian optimization algorithm is used to calculate the probability distribution of cache blocks in each node in order to equalize the node temperature. Secondly, the structure of TB-NUCA is designed. Finally, comparative experiments were conducted under random, transpose-2, and shuffle traffic patterns. The experimental results reveal that, compared with the classical NUCA mapping mechanism (S-NUCA), TB-NUCA can increase the mean-time-to-failure (MTTF) of routers by up to 28.13% while reducing the maximum temperature, average temperature, and standard deviation of temperature by a maximum of 4.92%, 4.48%, and 20.46%, respectively.

Modern embedded systems are packed with dedicated field-programmable gate arrays (FPGAs) to accelerate the overall system performance. But the main drawback in using FPGA as a reconfigurable system is that a lot of reconfiguration overheads are generated in the reconfiguration process. The reconfiguration overheads are mainly because of the configuration data being fetched from the off-chip memory and also due to the improper management of tasks during execution. This work focusses mainly on the prefetch heuristics, reuse technique, and the available memory hierarchy to provide an efficient management of tasks over the available resources. This short communication proposes a new optimal replacement policy which reduces the overall time and energy reconfiguration overheads for static systems in their subsequent iterations. It is evident from the results that most of the time and energy reconfiguration overheads are eliminated.

Out-of-box methods can provide strict isolation between the security tool and the target virtual machine (TVM), so they have strong anti-jamming abilities. Current monitoring methods are mostly based on memory snapshots at a time point or a fixed period. Due to the randomness of processes and the discontinuity of monitoring methods, methods based on time point or fixed period snapshots that security tools used to monitor processes may result in a high leakage rate. The real-time monitoring method can be used to resolve this problem. However, all current real-time monitoring methods require a ready monitoring set, and their monitoring range is strictly limited. They are only effective for the inherent objects within the ready set and ineffective for the random processes. This paper presents real-time monitoring of virtual machine processes (RMVP), a real-time monitoring method to monitor a random process in the TVM. First, the RMVP monitors process switch by capturing the switch of kernel stack base addresses outside the TVM in real time. Then, it extracts raw memory of the current process through the memory mapping technology that adopts caching mechanism and multi-task concurrent execution strategy. Finally, the RMVP translates raw memory into high-level semantics according to a semantic knowledge base constructed offline. The RMVP can monitor random processes in real time and overcome the challenge of process randomness. The experimental results show that the capture rate of the random process is over 95% and the capture delay is in the range of 2.3~3.3 ms. In addition, the RMVP is especially effective for detecting the processes hidden by rootkits.

Perceptrón memoria de correlación multicapa para predecir la violencia sistemática contra la mujer por su pareja en la Sierra del Perú Multilayer Perceptron correlation memory to predict systematic violence against woman by their partner in the Sierra of Peru María Estela Ponce Aruneri y Erwin Kraenau Espinal Universidad Nacional Mayor de San Marcos, Facultad de Ciencias Matemáticas. Lima 01 DOI: https://doi.org/10.33017/RevECIPeru2013.0008/ Resumen En este trabajo se muestra que el modelo perceptrón memoria de correlación multicapa permite predecir el tipo de violencia que sufren las mujeres mayores de 14 años unidas o alguna vez unidas, residentes habituales en las viviendas circundantes de los Centros de Emergencia Mujer ubicados en la sierra del Perú; así como asociaciones importantes entre algunos estilos de crianza, relaciones familiares y percepciones acerca de los roles de género, con el tipo de violencia que ejerce el esposo/ compañero. Utilizamos 1126 casos de la base de datos proporcionada por el Ministerio de la Mujer y Poblaciones Vulnerables (MIMP); para los que se construyeron catorce variables de entrada, una que se refieren a estilo de crianza recibido, tres a relaciones familiares, nueve sobre percepciones acerca de los roles de género y una referida al ámbito geográfico; siete variables de salida que se refieren al tipo de violencia contra la mujer por parte de su pareja o ex –pareja. Para la etapa de diseño del modelo perceptrón memoria de correlación y entrenamiento de la red aplicamos el algoritmo de retropropagación (backpropagation), la función de activación utilizada para este caso fue sigmoidal (logística), calculamos el error cuadrático para evaluar el error cometido por la red en cada patrón(observación); y finalmente regla delta generalizada para modificar pesos y umbrales. Se elaboraron dos programas en Matlab, para aplicar el modelo perceptrón memoria de correlación multicapa con una y dos capas ocultas. El modelo perceptrón memoria de correlación multicapa, con dos capas ocultas proporciono mejores resultados, 80.34% de predicciones correctas; y muestra que la violencia familiar y la percepción acerca del rol de género son factores importantes en la predicción del tipo de violencia que padece la mujer unida o alguna vez unida por su pareja, y que reside en la sierra del Perú. Descriptores: Memorias de Correlación, perceptrón multicapa, predicciones, violencia contra la mujer. Abstract In this research shows that the correlation model memory multilayer perceptron to predict the type of violence experienced by women over 14 have ever joined or united, ordinarily resident in the houses surrounding the Women's Emergency Centers located in the sierra del Peru, as well as significant associations between certain parenting styles, family relationships and perceptions about gender roles, with the kind of violence exercised by the husband / partner. We use 1126 cases of women from the database provided by the Ministry of Women and Vulnerable Populations (MIMP); for which fourteen input variables were built, one relating to parenting style received, three family relationships, nine out of perceptions about gender roles and one referring to the geographical, seven output variables relate to the type of violence against women by their partner or ex-partner. For the design stage memory model and correlation perceptron network training apply the backpropagation algorithm, the activation function used in this case was sigmoidal (logistic), we calculated the mean square error to evaluate the error committed by the network in each pattern (observation), and finally generalized delta rule to change weights and thresholds. Two programs were developed in Matlab to implement the memory mapping model multilayer perceptron with one and two hidden layers. The model multilayer perceptron correlation memory with two hidden layers I provide better results, 80.34% of correct predictions, and shows that family violence and perceptions about gender roles are important factors in predicting the type of violence that women have ever joined or united by their partner, and reside in the sierra of Peru. Keywords: Correlation memories, multilayer perceptron, predictions, violence against women

Актуальність теми. Розвиток інформаційних технологій з кожним роком займає все більше значення у багатьох галузях людської життєдіяльності, це стимулює технічний прогрес у цілому і супроводжується створенням великої кількості даних. Завдяки цьому, все з більшою швидкістю розвиваються такі напрями інформаційних технологій як машинне навчання, штучний інтелект та аналіз даних. Але не у кожної компанії є можливість найняти собі такого спеціаліста або скористатись послугами провайдерів хмарних обчислень, тому економні методи аналізу даних стають все більш цікавими для невеликих підприємств чи приватних підприємців. Мета дослідження. Метою є побудова архітектурного рішення для аналізу великих масивів даних з мінімальним використанням оперативної пам’яті комп’ютера, а також реалізація веб додатку з використанням пропонованої архітектури. Для реалізації поставленої мети були сформульовані наступні завдання: дослідити існуючі методи аналізу даних; дослідити методи швидкого завантаження файлів на сервер; дослідити методи роботи з архівами даних; дослідити методи та формати зберігання великих обсягів даних на стороні серверу; дослідити бібліотеки для аналізу масивів даних; розробити експериментальне архітектурне рішення, використовуючи Python Jupyter Notebook; розробити мінімальні клієнтські та серверні компоненти для підтвердження ефективності запропонованої архітектури. Об’єкт дослідження – аналіз великих масивів статистичних даних. Предмет дослідження – аналіз даних на пристроях з низькими технічними можливостями. Наукова новизна: Наукова новизна полягає у розробці архітектмінімізуючи при цьому використання оперативної пам’яті, що призводить до більш дешевих обчислень ніж у аналогічних рішень. Практичне значення отриманих результатів визначається тим, що розроблено програмний продукт, який демонструє основні переваги запропонованого архітектурного рішення. Зв’язок роботи з науковими програмами, планами, темами: дисертація виконувалась в рамках ініціативної теми кафедри АСОІУ «Методи та технології в задача пошуку та збереження даних». Апробація: основні положення роботи доповідались і обговорювались на 5-й Всеукраїнській науково-практичній конференції молодих вчених та студентів «Інформаційні системи та технології управління»(ІСТУ-2020): Матеріали наукової конференції студентів, магістрантів та аспірантів, м. Київ, 27 листопада 2020. Публікації: Архітектурне рішення для обробки великих обсягів статистичних даних на пристроях з низькими технічними можливостями / Вальчук Д.В., Головченко М.М. // V Всеукраїнська науково-практична конференція молодих вчених та студентів «Інформаційні системи та технології управління»(ІСТУ-2020): Матеріали наукової конференції студентів, магістрантів та аспірантів, м. Київ, 27 листопада 2020.урного рішення, яке базується на використанні жорсткого диску серверного комп’ютера Actuality of theme. The development of information technology is becoming increasingly important in many areas of human life, which provides technical progress in general and is accompanied by the creation of large amounts of data. Due to this, such areas of information technology as machine learning, artificial intelligence and data analysis are developing more and more rapidly. Outside of each company, the possibility of hiring such specialists or using the services of a cloud computing provider, as well as economic methods of analysis are becoming increasingly interesting for small industrial private industrial enterprises. The aim of the research. The goal is to build an architectural solution for the analysis of large data sets with minimal use of computer RAM, as well as the implementation of a web application using the proposed architecture. To achieve this goal, the following tasks were formed: explore existing methods of data analysis; explore methods of fast uploading files to the server; explore methods of working with data archives; explore methods and formats for storing large amounts of data on the server side; develop an experimental architectural solution using Python Jupyter Notebook; develop minimum client and server components to confirm the proposed architecture. The object data analysis. The subject data analysis on devices with low technical capabilities. Scientific Novelty: The scientific novelty lies in the development of an architectural solution based on the use of the server's hard disk while minimizing the use of RAM, which leads to cheaper calculations than similar solutions. The practical value of the results is a software product which demonstrates the main advantages of the proposed architectural solution. Relationship with scientific programs, plans, topics: the dissertation was carried out in the scope of initiative theme of the ASOIU department “Methods and technologies in the task of searching and storing data”. Testing: The main provisions of the work were reported and discussed at the 5th All-Ukrainian scientific-practical conference of young scientists and students "Information systems and management technologies" (ISTU-2020): Proceedings of the scientific conference of students, undergraduates and graduate students, Kyiv, November 27, 2020. Articles: Architectural solution for processing large volumes of statistical data on devices with low technical capabilities / Valchuk D.V., Golovchenko M.M. // V All-Ukrainian scientific-practical conference of young scientists and students "Information systems and management technologies" (ISTU-2020): Proceedings of the scientific conference of students, undergraduates and graduate students, Kyiv, November 27, 2020.

This article seeks to explore the quantum notion that to ‘see’ an entanglement is to break it in the context of an ‘experiment’ regarding the ongoing impact of traumatic political memory on the present. The analysis is a product of collaboration over the past four years between the two authors, one a scholar of international relations, the other a therapeutic practitioner with training in medical physics. Our focus is the conceptual claim that ‘seeing’ breaks an entanglement rather than the experiment itself. The first section explores a broad contrast between classical and quantum measurement, asking what this might mean at the macroscopic level. The second section categorizes Wendt’s claim about language as a form of expressive measurement and explores the relationship to discourse analysis. The third section explores the broad contours of our experiment and the role of a somewhat different form of non-linear expressive measurement. In the final section, we elaborate the relationship between redemptive measurement and breaking an entanglement, which involves a form of ‘seeing’ that witnesses to unacknowledged past trauma. Publisher PDF

Modern software development in the automotive domain would be unthinkable without leveraging reusable software components. Such generic software components have to be configured and tailored for each specific target application. Nowadays, complexity has reached a point where developing generic software components and manually adapting each component for each variant in the product family is error-prone and no longer economically feasible. In this article we propose an engineering framework for automated adaptation of generic software components which focuses on temporal and spatial integrity. The framework is built around a generic methodology and leverages specialized software tools to determine an allocation of software components to the resources of an embedded system and to ensure memory integrity. We use a quadcopter example, executed on the Infineon AURIX TC277 processor under the AUTOSAR operating system to illustrate our approach .

Given the increase in cache capacity over the past few decades, cache access efficiency has come to play a critical role in determining system performance. To ensure efficient utilization of the cache resources, non-uniform cache architecture (NUCA) has been proposed to allow for a large capacity and a short access latency. With the support of networks-on-chip (NoC), NUCA is often employed to organize the last level cache. However, this method also hurts cache access fairness, which denotes the degree of non-uniformity for cache access latencies. This drop in fairness can result in an increased number of cache accesses with overhigh latency, which leads to a bottleneck in system performance. This paper investigates the cache access fairness in the context of NoC-based 3-D chip architecture, and provides new insights into 3-D architecture design. We propose fair-NUCA (F-NUCA), a co-design scheme intended to optimize cache access fairness. In F-NUCA, we strive to improve fairness by equalizing cache access latencies. To achieve this goal, the memory mapping and the channel width are both redistributed non-uniformly, thereby equalizing the non-contention and contention latencies, respectively. The experimental results reveal that F-NUCA can effectively improve cache access fairness. When F-NUCA is compared with the traditional static NUCA in a simulation with PARSEC benchmarks, the average reductions in average latency and latency standard deviation are 4.64%/9.38% for a $4 \times 4 \times 2$ mesh network, as well as 6.31%/13.51% for a $4 \times 4 \times 4$ mesh network. In addition, a 4.0%/6.4% improvement in system throughput can be achieved for the two scales of mesh networks, respectively.

This paper deals with assessing the integrity of composite structures via modal acoustic emission (MAE) technique. It is a continuity of the paper “On the modal acoustic emission of composite structures”, published last year by the authors in the same journal. To improve the reliability level of this technique (as it is the case of the other nondestructive techniques), exploring various innovative processing techniques of the collected data is required. Unfortunately, this task undergoes a huge volume of data, where its management (processing, reuse, etc.) should be achieved as well as possible. Hence, performing an efficient processing of the large data sets that can be generated via MAE, during the composite structures health monitoring, is a challenging topic. This study concerns the development of an algorithmic tool for resolving the problem of memory saturation, which can be encountered when working with such large data sets. It is a first step towards Big Data based solutions, launched recently by the authors’ team. A case of study is discussed, showing the robustness of the already implemented algorithmic tool.