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Through-silicon vias (TSVs) are required for transmitting signals among different dies for the 3-D integrated circuit (IC) technology. The significant silicon areas occupied by TSVs bring critical challenges for 3-D IC placement. Unlike most published 3-D placement works that only minimize the number of TSVs during placement due to the limitations in their techniques, this paper proposes a new 3-D cell placement algorithm that can additionally consider the sizes of TSVs and the physical positions for TSV insertion during placement. The algorithm consists of three stages: 1) 3-D analytical global placement with density optimization and whitespace reservation for TSVs; 2) TSV insertion and TSV-aware legalization; and 3) layer-by-layer detailed placement. In particular, the global placement is based on a novel weighted-average (WA) wirelength model, giving the first published model that can outperform the well-known log-sum-exp wirelength model theoretically and empirically. Also, a scheme is proposed to enhance the numerical stability of the WA wirelength model. Furthermore, 3-D routing can easily be accomplished by traditional 2-D routers since the physical positions of TSVs are determined during placement. Experimental results show the effectiveness of our algorithm. Compared with state-of-the-art 3-D cell placement works, our algorithm can achieve the best routed wirelength, TSV counts, and total silicon area, in shortest running time.

Al0.22Ga0.78As/In0.18Ga0.82As/Al0.22Ga0.78As double heterojunction high electron mobility transistors (DH-HEMTs) with gate structures of traditional planar gate (PG), one-stage gamma-gate (1SΓG) and two-stage gamma-gate (2SΓG) formed by using the Al0.22Ga0.78As/In0.49Ga0.51P etch-stop layers (ESL) are simulated and presented in this work. Based on this proposed ESL structure design, the fabrication and implementation of studied DH-HEMT device with 1SΓG and 2SΓG could be expected. Both ΓG-structure devices show the better electric field property compared to PG-device. Simulated results reveal that there are no significant differences in common-source voltage-current characteristics among all studied devices. The obtained drain current density and transconductance of all studied devices are about 220 mAmm-1and 265 mSmm-1. However, the current stability of ΓG-devices with larger bias operation would be improved due to its edge-effect of ΓG extended-region. In addition, the electric field intensity under the gate-footprint is effectively reduced by both studied ΓG structures. The electric field peak value of PG-device is 498 kV cm-1, and it would be reduced down to about 210 kVcm-1and 178 kVcm-1for 1SΓG- and 2SΓG-device, respectively. On the other hand, some frequency property dropping is observed from studied device with 1SΓG or 2SΓG due to the side-edge extension of ΓG-device would create the additional parasitic capacitance. The obtained cut-off frequencies are 15 GHz, 10.5 GHz and 10 GHz for PG-, 1SΓG- and 2SΓG-device (at VGS=+5 V and VGS=-0.75 V), respectively.

In this work, a combined process for simultaneously manufacturing nanoporous silicon (NPS) and its metallization was present. The key point is the utilization of adjust electrolyte of silver nitrate and the electroplating timing after the NPS etching process. The current-control mode was used to prepare NPS membrane and the obtained pore-size and pillar-depth were about 0.5 μm and 140 μm, respectively. For clarify the metallization quality of studied process, the semiconductor analyzer was utilized to measured current-voltage (IV) characteristic. Compared to NPS with conventional electroplating process, the contact properties of fabricated sample would be effectively improved by the proposed method. The obtained IV characteristic of sample with combined process shows a larger turn-on current about 277 times than other samples.

In this paper, an investigation of the static/dynamic performance of dual-emitter phototransistors (DEPTs) as an electrooptical switch was made. In the static case, the measured optical gains (the collector photocurrents) of DEPTs operated at a 12.5-muW optical power have been enhanced from 13.7 to 20.2 (88 to 129 muA) due to an emitter-induced gain high (EIGH) from photocurrent modulation. For DEPTs as an electrooptical switch, the EIGH from photocurrent modulation and the emitter-induced gain effect from junction-voltage modulation dominate the dynamic operation. In the case of continuous light input, good bistable-state output characteristics can be realized with an electrical clock signal. When the switch is operated with a 2-V supply voltage and a 10-kOmega load resistance, the stable electrical-logic swing (ELS) is 0.41 V for a 1-V/1-kHz clock signal. Electrical inputs of 5-, 10-, and 50-kHz clock signals are also employed to achieve outputs with increased ELSs of 1.18, 1.19, and 1.3 V, respectively. An optical inverter is realized. When two clock signals, an electrical input and an optical input, are employed, DEPTs are operated as a tristable-state switch.

The influence of gate metal with thermal annealed process adopt to control the distance between gate and channel on pseudomorphic Al0.24Ga0.76As/ In0.22Ga0.78As double heterojunction high electron mobility transistors (DH-HEMTs) were studied. Compared to device with gate-recess process, the distance of gate-to-channel could be controlled through the thermal annealed process and therefore exhibit a lower series resistance. Measured transconductance of 150 mS/mm and an open- drain voltage gain of 136 for the DH-HEMT with an as deposited gate are enhanced to 175 mS/mm and 160 for the DH-HEMT with a 330-{degree sign}C annealed gate. Good device linearity is also obtained with a low second-harmonic to fundamental ratio of 3.55 %. In addition, good microwave performances such as unit-current gain- and maximum power gain- frequency were also obtained from devices with gate-annealed process.

N-p-n InGaP/GaAs Dual-Emitter heterojunction phototransistor (DEPT) with/without InGaP-passivation layer have been fabricated to investigate the influence of surface leakage on the device optical performance. The comparison between DEPT with a voltage-biased emitter and HPT with a voltage-biased base is also included. There are four (three) operating regions appearing in the optical characteristics of the DEPT (HPT): negative-saturation, negative-tuning, positive-tuning, and positive-saturation (cut-off, tuning, and saturation) regions. The InGaP-passivated DEPT with the extrinsic base surface passivated by InGaP, exhibits the maximum optical gains of 46.57, 46.86 and 47.39 while the non-passivated one shows those of 32.02, 33.55 and 33.57 under the optical powers of 8.62, 13.2 and 17.5 μW, respectively. However, the optical gains are only in the range of 0.93~2.0 (0.83~1.64) for the InGaP- passivated HPT (non-passivated HPT) for all the illuminating conditions.

N–p–n InGaP/GaAs Dual-Emitter HPTs (DEHPTs) with and without extrinsic base surface passivation were fabricated to investigate the influence of the surface leakage on the device’s optical performance. There are four operating regions appearing in the output characteristics of DEHPTs under illumination: negative-saturation, negative-tuning, positive-tuning and positive-saturation regions. The InGaP-passivated DEHPT (P-DEHPT), i.e. DEHPT with the extrinsic base surface passivated by InGaP, exhibits the maximum optical gains of 46.57, 46.86 and 47.39 while the non-passivated one (NP-DEHPT) shows ones of 32.02, 33.55 and 33.57 for optical powers of 8.62, 13.2 and 17.5 μW, respectively. However, the NP-DEHPT exhibits the larger peak gain-tuning efficiencies of 37.35, 41.03 and 44.10 compared to 12.76, 13.72 and 16.01 V −1 for the P-DEHPT for optical powers of 8.62, 13.2 and 17.5 μW, respectively. The better tuning efficiency makes the NP-DEHPT a possible low optical power optoelectronic application.

We report on the InGaP/GaAs dual-emitter heterojunction phototransistors (DEPTs) with an emitter biased using a voltage for comparison to heterojunction phototransistors (HPTs) with a floating base operated in the p-i-n and transistor modes and to the HPTs with a base biased using a voltage. The optical gain of the DEPT is presented to be tunable with both of the voltage applied to the emitter and the incident optical power. On the contrary, a conventional HPT's configuration does not simultaneously exhibit both. The power-tunable optical gain is available when the base of the HPT is floated. Otherwise, the voltage-tunable optical is expected for the HPT with a voltage biased base. Experimental results show that (1) the HPT with a voltage biased base exhibits a gain-tuning efficiency of 4.4 V- 1 and (2) the DEPT with an emitter biased using a voltage exhibits a gain-tuning efficiency of 43.4 V-1.

This paper reports on InGaP/GaAs heterojunction bipolar transistors (HBTs) with a sulfur-treated base layer, which are then compared to InGaP/GaAs HBTs with an InGaP-passivated base layer. Experimental results reveal that the improvement in base leakage current for InGaP-passivated HBTs is due to the inherent low surface recombination velocity associated with an InGaP layer while it is the electronic modification of the GaAs surface for sulfur-treated HBTs. The maximum dc current gain available is β = 75 with a base sheet resistance of R B = 220 Ω / □ for a sulfur-passivated HBT. The sulfur-passivated HBTs also exhibit very good linearity over a wide collector current range of 10−5 to 10−1 A. Furthermore, detailed sulfur treatment conditions and effects on device performances including post-treatment stability are investigated.

Fabrication, characterization, and modeling of three-terminal (3T) heterojunction phototransistors (HPTs) using an InGaP layer for passivation (called P-HPTs) compared with similar nonpassivated devices (called NP-HPTs) were reported. Effects of the base passivated by the InGaP layer on devices optical and electrical performance were investigated. In addition to improving the dc current gain in the small current regime, the photocurrent (I/sub ph/) and responsivity from the p-i-n diode formed by the base, collector, and subcollector are also enhanced in a P-HPT. The measured optical gains are 45 and 27 for a P- and an NP-HPT under 8.62-/spl mu/W optical injection operated as a two-terminal (2T) device with a floating base. When the base bias is applied from a voltage source, both 3T P- and NP-HPTs exhibit degraded optical gains. Although a voltage source applied to the base can be used to push the operating point of a heterojunction bipolar transistor to a higher collector current where the current gain is higher, only a small portion of the photocurrent generated within the base-collector region is injected across the base-emitter junction to be amplified. When the base of an HPT is biased using a current source, the I/sub ph/ and enhanced dc current gain mainly determine both collector photocurrent and optical gain. Thus, a P-HPT biased using a current source shows the best optical performance. Furthermore, the conventional Ebers-Moll equivalent-circuit model was extended to provide simulated results in good agreement with experiment.

An edge effect caused by a spontaneous bias on the anodizing current density at the edged area is found during electrochemical etching. On the porous silicon films formed by the electrochemical etching method, evidence of the edge effect appearing on the photoluminescence pattern is first proposed in the study. With an appropriate electrolytic cell design where a halo baffle is placed between the anode and cathode as a barrier to reactant flux on the outer ring, the flux at the edge would be curved. It results in various degrees of electrochemical reactions and various porous structures on the silicon wafer. The experimental results propose an exhaustive view at the edge area in electrochemical etching process, and also propose an optional selection for free-mask patterning technology of porous silicon.

Newest manufacturing technologies with feature sizes smaller than 20nm and FinFET devices have favored more restrictive design rules for manufacturability while suffering from electrical limitations of electromigration (EM) and variability. Designers can no longer reap the benefits in power, performance and area by simply relying on feature size miniature with contemporary design techniques. This work illustrates the importance of design and manufacturing technology co-optimization. Limitations in lithography has led to slower reduction in metal and VIA shape spacing than critical dimensions, which prompts for co-optimization in metallization stack, power mesh planning, standard cell designs and placement algorithms. New routing algorithms and parasitics modeling are required to achieve improved design performance under sky-rocketing metal resistance especially at lower metal levels. Ever-lowering maximum current limits due to EM has prompted new approaches in placement optimization to counteract the potential explosion in EM violations. Adoption of FinFET has allowed ultra-low Vdd designs, which requires careful consideration of Vth offerings that allow proper trade-off between variability, area and power efficiency.

The electrolyte stirring method of anodization etching process for manufacturing porous silicon (PS) is reported in this work. Two experimental setups of nature air stirring (PS-ASM) and electrolyte stirring (PS-ESM) are employed to clarify the influence of stirring mechanisms on electrochemical etching process. Compared to traditional fabrication without any stirring apparatus (PS-TM), a large plateau region of PS surface structure is obtained from samples with both stirring methods by the 3D-profiler measurement. Moreover, the light emission response is also improved by both proposed electrolyte stirring methods due to the cycling force in electrolyte could effectively enhance etch-carrier distribution while the electrochemical etching process is made. According to the analysis of statistical calculation of photoluminescence (PL) intensity, lower standard deviations are obtained from PS-samples with studied stirring methods, i.e. the uniformity of PL-intensity is effectively improved. The calculated deviations of PL-intensity are 93.2, 74.5 and 64, respectively, for PS-TM, PS-ASM and PS-ESM., {"references":["L. T. Canham, \"Silicon quantum wire array fabrication by\nelectrochemical and chemical dissolution of wafers,\" Appl. Phys. Lett.,\nvol. 57, pp. 1046-1048, July 1990.","P. McCord, S. L. Yau and A. J. Bard, \"Chemiluminescence of anodized\nand etched silicon: evidence for a luminescent siloxene-like layer on\nporous silicon,\" Science, vol. 257, pp. 68-69, Jul. 1992.","P. Fauchet, \"Photoluminescence and electroluminescence from porous\nsilicon,\" J. Lumin., vol. 257, pp. 294-309, Oct. 1996.","A. G. Cullis, L. T. Canham and P. D. J. Calcott, \"The structural and\nluminescence properties of porous silicon,\" J. Appl. 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Huang, \"High-performance integrated\ninductor and effective crosstalk isolation using post-CMOS selective\ngrown porous silicon (SGPS) technique for RFIC applications,\" Solid\nState Electron., vol. 51, pp. 989-994, Jun. 2007.\n[15] L. T. Canham, W. Y. Leong, T. I. Cox and L. Taylor, \"Efficient visible\nelectroluminescence from highly porous silicon under cathodic bias,\"\nAppl. Phys. Lett., vol. 61, pp. 2563-2565, Sep. 1992.\n[16] J. C. Lin, P. W. Lee and W. C. Tsai, \"Manufacturing method for n-type\nporous silicon based on Hall effect without illumination,\" Appl. Phys.\nLett., vol. 89, pp. 12119-1-3, Sep. 2006.\n[17] A. Richter, P. Steiner, F. Kozlowski and W. Lang, \"Current-induced light\nemission from a porous silicon device,\" IEEE Electron Device Lett., vol.\n12, pp. 691-692, Dec. 1991.\n[18] J. Sarahy, S. Shih, K. Jung, C. Tsai, K. H. Li, D. L. Kwong, J. C.\nCampbell, S. L. Yau and A. J. Bard, \"Demonstration of\nphotoluminescence in nonanodized silicon,\" Appl. Phys. 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Through-silicon vias (TSVs) are required for transmitting signals among different dies for the three-dimensional integrated circuit (3D IC) technology. The significant silicon areas occupied by TSVs bring critical challenges for 3D IC placement. Unlike most published 3D placement works that only minimize the number of TSVs during placement due to the limitations in their techniques, this paper proposes a new 3D cell placement algorithm which can additionally consider the sizes of TSVs and the physical positions for TSV insertion during placement. The algorithm consists of three stages: (1) 3D analytical global placement with density optimization and whitespace reservation for TSVs, (2) TSV insertion and TSV-aware legalization, and (3) layer-by-layer detailed placement. In particular, the global placement is based on a novel weighted-average wirelength model, giving the first model in the literature that can outperform the well-known log-sum-exp wirelength model theoretically and empirically. Further, 3D routing can easily be accomplished by traditional 2D routers since the physical positions of TSVs are determined during placement. Compared with state-of-the-art 3D cell placement works, our algorithm can achieve the best routed wirelength, TSV counts, and total silicon area, in shortest running time.

A modern chip often contains large numbers of predesigned macros (e.g., embedded memories, IP blocks) and standard cells, with very different sizes. The fast-growing design complexity with large-scale mixed-size macros and standard cells has caused significant challenges to modern circuit placement. Analytical algorithms have been shown to be most effective for standard-cell placement, but the problems with the rotation and legalization of large macros impose intrinsic limitations for analytical placement. Consequently, most recent works on mixed-size placement resort to combinatorial macro placement. Instead, this paper presents the first attempt to resolve the intrinsic problems with a unified analytical approach. Unlike traditional analytical placement that uses only wire and density forces to optimize the positions of circuit components, we present a new force, the rotation force, to handle macro orientation for analytical mixed-size placement. The rotation force tries to rotate each macro to its desired orientation based on the wire connections on this macro. A cross potential model is also proposed to increase the rotation freedom during placement. The final orientation of each macro with legalization consideration is then determined by mathematical programming. A macro flipping force is also proposed to determine the flipping orientation of each macro at the end of global placement. Compared with start-of-the-art mixed-size placement approaches (such as FLOP, CG, and MP-tree), our approach achieves the best average wirelength efficiently.

In this study, the thermal properties of silicon samples with surfaces of porous and geometrical formation were reported. The etching methods of anodization chemical and heated KOH were utilized to perform the studied nano porous silicon (NPS) and pyramidal, respectively. Compared with usual surface formation of ordinary silicon sample, the larger surface to volume ratios were obtained from the fabricated NPS and pyramidal silicon devices. For the thermal applications such as thermal sensor and microheater, the etching profiles and surface to volume ration of studied were clarified by SEM measurement. Furthermore, the differential scanning calorimetry (DSC) was used to evaluate the thermal dissipation properties of studied samples.

In this work, we report a metal-splitting field plate gate on heterojunction doped-channel field effect transistors (HDCFETs) with an application of GaAs-bulk. Experimentally, a HDCFET with a gate-metal length of 0.4 mum, a field-plate length of 0.6 mum, and a bulk thickness of 120 nm was successfully fabricated for comparing to that with a 1-mum traditional planar-gate. The current density (451 mA/mm), transconductance (225 mS/mm), breakdown voltages (VBD(DS)/VBD(GD)=22/-25.5 V), gate-voltage swing (2.24 V), unity current-gain and power-gain frequencies (ft/fmax=17.2/32 GHz) are improved as compared to those of 1-mum gate device without field plates. At 1.8 GHz with a VDS of 4.0 V operation, a maximum power-added efficiency (PAE) of 36% with an output power of 13.9 dBm and a power gain of 8.7 dB was obtained. Saturated output power and linear power gain are 316 mW/mm and 13 dB, respectively.

This paper reports on a four-terminal dual-emitter heterojunction phototransistor (4T-DEPT) with a base biased by current source in comparison with a three-terminal dual-emitter heterojunction photoreansistor (3T-DEPT) without the additional current bias. While only voltage can be used to tune the optical performance of the 3T-DEPT, two kinds of operation modes, voltage- (VE21) and current- (IBdc) control modes, are considered for the 4T-DEPT. In addition to the power- and voltage-tunable optical gains, current-tunable one is also available in the 4T-DEPT operation. When the 4T-DEPT operates under the incident optical power (Pin) of 0.423 μW, it shows the maximum current-dependent gain-tuning efficiency of 62.66 μA-1 at VE21 = 0.06 V and IBdc = 0.001 μA. However, it is only 45.03 V-1 for the maximum voltage-dependent gain-tuning efficiency at VE21 = 0.06 V and IBdc = 0.25 μA.

not Available.

Temperature-dependent dark and optical characteristics of the InGaP/GaAs heterojunction phototransistors (HPTs) with and without sulfur treatment are studied. As compared to the HPT without (NH 4 ) 2 S treatment (HPT A), treatment at 50°C for 20 min leads to a reduced p-i-n dark current (/dark) and a reduced collector dark current (IC dark ) for the HPT (HPT D) in the emitter-floated and base-floated configurations, respectively. Moreover, the effective reduction of the surface defects also induces an enhanced p-i-n photocurrent (I ph ). The enhanced I ph combined with the promoted dc current gain results in an enhanced optical gain (G) and signal-to-noise ratio (SNR). For HPT A (D) under P in = 107.6 nW at 298 K, the G is 1.42 (20.3) while the SNR is 42 (94) dB. Experimental results indicate that the treated HPTs, compared to the untreated one, are more sensitive to low-power illumination.

InGaP/GaAs dual-emitter heterojunction phototransistors (DEPTs) with an emitter biased using a voltage is reported for comparison to heterojunction phototransistors (HPTs) with a floating base operated in the p–i–n and transistor modes and to the HPTs with a base biased using a voltage. Although the power- and voltage-tunable optical gains are expected when the base of the HPT is floated and biased using a voltage, respectively, a conventional HPT's configuration does not simultaneously exhibit both. On the contrary, the optical gains of the DEPT can be tuned by both the voltage applied to the emitter and the incident optical power. Experimental results show that (1) the power-tunable optical gains are in the range of 11–29 as determined by the incident optical power upon the HPT with a floating base, (2) the small optical gains tuned by a voltage are 0.83–1.6 with a gain-tuning efficiency of 4.4 V-1 for the HPT with a base electrode, and (3) the DEPT with an emitter biased using a voltage exhibits an enhanced optical gain, with a gain-tuning efficiency of 43.4 V-1, when compared with the HPT with a floating base. Finally, a new concept of current-sharing effects in the base region is introduced to explain power- and/or voltage-tunable characteristics with good agreement found.