Search

We present and discuss parameters of a high dynamic range (HDR) image sensor with LED flicker mitigation (LFM) operating in automotive temperature range. The total SNR (SNR including dark fixed pattern noise), of the sensor is degraded by floating diffusion (FD) dark current (DC) and dark signal non-uniformity (DSNU). We present results of FD DC and DSNU reduction, to provide required SNR versus signal level at temperatures up to 120 &deg, C. Additionally we discuss temperature dependencies of quantum efficiency (QE), sensitivity, color effects, and other pixel parameters for backside illuminated image sensors. Comparing +120 &deg, C junction vs. room temperature, in visual range we measured a few relative percent increase, while in 940 nm band range we measured 1.46x increase in sensitivity. Measured change of sensitivity for visual bands&mdash, such as blue, green, and red colors&mdash, reflected some impact to captured image color accuracy that created slight image color tint at high temperature. The tint is, however, hard to detect visually and may be removed by auto white balancing and temperature adjusted color correction matrixes.

Differential binary pixel technology is a threshold-based timing, readout, and image reconstruction method that utilizes the subframe partial charge transfer technique in a standard four-transistor (4T) pixel CMOS image sensor to achieve a high dynamic range video with stop motion. This technology improves low light signal-to-noise ratio (SNR) by up to 21 dB. The method is verified in silicon using a Taiwan Semiconductor Manufacturing Company’s 65 nm 1.1 μm pixel technology 1 megapixel test chip array and is compared with a traditional 4 × oversampling technique using full charge transfer to show low light SNR superiority of the presented technology.

A 2 micrometers BiCMOS process module has been developed for incorporation into existing high performance 2-phase CCD processes, to enable integration of digital and analog circuits on- chip with the CCD image sensor. The modular process architecture allows the integration of CMOS, NPN bipolar or BiCMOS circuits without affecting the baseline CCD characteristics. A design of experiments approach was employed using process and device simulation tools and selected physical experiments, to optimize CMOS and NPN device performance and process latitude. Both enhancement and depletion mode Poly-1 and Poly-2 CMOS devices were realized and demonstrated good long channel behavior down to 1.6 micrometers drawn. A 12 V, 2.5 GHz, low collector resistance NPN was also produced. Experimental process splits were used to demonstrate and verify that the CMOS and NPN process module incorporation did not affect the CCD device characteristics or yield. CMOS circuit performance was found to be comparable to that of a standard 2 micrometers CMOS process. Finally, a trilinear sensor with on-chip timing generation and correlated double sample was designed and fabricated. To our knowledge this is the first demonstration of high performance CCD, 2 micrometers CMOS, and an isolated vertical NPN, integrated on the same chip.