44 results on '"Michael S. Schlansker"'
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2. A Distributed Control Path Architecture for VLIW Processors.
3. Configurable optical interconnects for scalable datacenters.
4. In Memory of Bob Rau.
5. ShiftQ: a bufferred interconnect for custom loop accelerators.
6. Embedded Computing: New Directions in Architecture and Automation.
7. Control CPR: A Branch Height Reduction Optimization for EPIC Architectures.
8. Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks.
9. Global Predicate Analysis and Its Application to Register Allocation.
10. Analysis Techniques for Predicated Code.
11. Critical path reduction for scalar programs.
12. Spill-free parallel scheduling of basic blocks.
13. Fast synchronization for chip multiprocessors.
14. Height reduction of control recurrences for ILP processors.
15. Acceleration of First and Higher Order Recurrences on Processors with Instruction Level Parallelism.
16. Sentinel Scheduling for VLIW and Superscalar Processors.
17. Code generation schema for modulo scheduled loops.
18. Register Allocation for Software Pipelined Loops.
19. Embedded Computer Architecture and Automation.
20. Bitwidth cognizant architecture synthesis of custom hardwareaccelerators.
21. Compiling for EPIC architectures.
22. Parallelization of loops with exits on pipelined architectures.
23. EPIC: Explicititly Parallel Instruction Computing.
24. Techniques for critical path reduction of scalar programs.
25. Challenges to Combining General-Purpose and Multimedia Processors.
26. Compilers for Instruction-Level Parallelism.
27. Parallelization of Control Recurrences for ILP Processors.
28. Sentinel Scheduling for VLIW and Superscalar Processors.
29. Parallelization of WHILE loops on pipelined architectures.
30. Guest Editors' Introduction.
31. High-performance ethernet-based communications for future multi-core processors.
32. The Cydram 5 Stride-Insensitive Memory System.
33. Systematically derived instruction sets for high-level language support.
34. A microprogramming language for the B-1726.
35. Cydra 5.
36. Techniques for critical path reduction of scalar programs
37. Parallelization of Control Recurrences for ILP Processors
38. The 2014 MICRO Test of Time Award Winners: From 1978 to 1992
39. Sentinel scheduling
40. Parallelization of WHILE loops on pipelined architectures
41. Control CPR
42. Acceleration of first and higher order recurrences on processors with instruction level parallelism
43. Sentinel scheduling for VLIW and superscalar processors
44. Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 33, Monterey, California, USA, December 10-13, 2000
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