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Multi-chip integrated Fan-Out packages and high I/O CSPs demands for higher routing density on wafer level. Due to that, the classical mask aligner lithography and photosensitive thin-film polymers used for BEOL reach its limits and new technologies and materials are necessary to generate lines and space down to two μm. These multi-metal layers set also higher demands on the mechanical properties of the materials. This paper presents a new excimer laser dual damascene process for ultra-fine routing for BEOL. Various materials like low cure temperature polyimide, BCB and 15-μm thick dry-film ABF material are structured by using an excimer laser stepper with a reticle mask to realize feature size below four μm with a high throughput. Micro-vias with a diameter below five μm are realized with high aspect ratio, which overcome the photolithographic limitations of the common used photosensitive thin-film polymers. The laser structuring allows to use innovative dielectric materials for WLP with optimized mechanical and electrical parameters for example inorganic filled polymers like dry-film ABF materials, which do not have to be photosensitive. The ablations depth per laser pulse and the cross-section of the ablated structures in dependence of the ablation parameters was investigated. The depth of embedded lines was set by number of pulses aside of integrated micro-vias. The lines and micro-vias were metallized with copper by galvanic process and the following CMP step removes the copper outside the ablated structures. The CMP removes only the copper and the metal of the seed-layer, which has the functions of an adhesion and barrier layer, stays intact. The under-etching of the conventional wet etch seed layer removal is a major problem for the fine line structures realized by the Laser Dual Damascene process. Due to that, the removal of the seed layer (usually titan) was investigated and it could be shown, that this layer can be removed by the excimer laser system. The stepper like system allows a sub-micron alignment accuracy with no need of a capture pad of the embedded lines. Test structures have been designed and fabricated with lines and spaces below 10 μm to demonstrate the dense multi-layer routing capability where the excellent reliability can be proven by air to air thermal cycling (from −55°C up to 125°C), current leakage and electro migration test.

Due to the excellent mechanical and electrical properties together with a cost efficient processing, the thin film polymers are used in various applications as an interlayer dielectric (ILD) material where the device is generally working at CMOS like low voltages. The integration of high voltages in the redistribution layer becomes more attractive in future to realize higher system miniaturization and integration. Regarding to this, the power transformations could be integrated on wafer level for direct support of the CMOS device without an additional power transformation unit. Also high voltage III-V semiconductor dies will be integrated in Fan-Out packages. Thin film polymers have the potential to meet the demands for high voltage applications like high break down voltage and low leakage current. Well established thin film polymers like CYCLOTENE (Benzocyclotbutene - BCB) show a break down voltage in the range of 530 V/um. Compared with inorganic passivation such as thermal SiO2 with a breakdown voltages from 400 up to 1000 V/µm the BCB is quiet compatible regarding to the processing windows of layer thickness from BCB in the range from 5 to 20 um. BCB has been widely adopted in electronic applications, due to its low dielectric constant, excellent chemical resistance, and high thermal stability (glass transition temperature, T g > 350 °C) after hard-curing. The BCB has several advantages, especially the good process capabilities such as a photo structuring capability, the low temperature and the vacuum-less processing, might be interesting to use it in high voltage applications. This paper contains the profound investigation of the behavior of BCB at high voltages. Regarding the usability analyzing for the BCB as high voltage dielectric the break down voltage behavior was estimated and a time depending breakdown voltage was observed regarding the duration of the voltage application. This behavior is not yet published in the literature for BCB. MIM structures with 1 mm and 5 mm radius were manufactured on wafer level for this investigation. The leakage current of a few pA is measured and the time-dependent dielectric breakdown (TDDB) is extracted from Current-Time characteristics and shown in Weibull-plots. The measurement shows a spectrum from 350 V/µm to 450 V/µm, depending of the duration of the voltage and the level of the applied voltage. It is found that there is an exponential linkage between field strength and the time till the breakthrough occurs. The break through at 450 V/µm occurs after about 280 seconds, while the sample at 350 V/µm withstands longer by the factor of 13. These results will a very important milestone for future high power applications.

The Fan-Out Wafer Level Packaging (FOWLP) is one of the biggest impacts for the microelectronics packaging today. Main benefit is the high potential in significant package miniaturization by the substrate-less short interconnects, which are realized by thin film metallization directly on the embedded dies instead of wire bonding or flip chip - bumps. This allows a cost effective and robust generation of multi-chip packages for System in Package (SiP) solutions. The thickness of the FOWLP's which are in volume production is in the range of 300 to 400 um [1]. The stacking of FOWLP packages for higher integrations set demands for thinner packages. Main limitation for high volume production of packages below 300 um is the handling of the thin substrates during the processing and the assembly of thin and also warped packages. This paper presents an innovative concept (Hybrid Fan-Out - hFO) for generation and handling of thin FOWLP substrates. A fundamental process change is realized in the so called chip-first approach which enables packages with thickness down to 30 um and below. The mold-first approach based on the assembly of dies on a thermal release tape, which is followed by the embedding process. The epoxy mold compound (EMC) substrate with the embedded dies is released from the carrier by peeling of the TRT and the redistribution layer (RDL) is generated. For the new approach the dies are directly assembled on a glass carrier with a die adhesive. The temperature stable bond of the dies to the glass carrier enables a thinning and backside processing of the EMC / glass carrier stack. The embedded dies are coincidently thinned together the mold material with the benefit, that no thinned dies are demanded for generation of thin packages and simplifies the assembly process. A RDL process is applied on the backside, which stabilize the ultra-thin package. A ultra-fine routing layer could realized because the stiff glass carrier inhibits any EMC substrate deformation or length changes, like it is happen by cure shrinkage or humidity uptake. The RDL on the front side is generated after the release from the carrier. The symmetric build-up structure with an EMC core and a double sided RDL allows to increase the number of routing layers, which are demanded for shielding and supply layers for RF applications. FOWLP packages with a thickness down to 50 um are demonstrated in this paper.

There is a strong demand to increase the routing density of the RDL to match the requirements for future microelectronic systems which are mainly miniaturization and performance. Photo-resists for structuring the metallization or acting as a mold for electroplating are common for very fine lines and spaces due to the developments in the front-end processing. For example chemical amplified Photo-resists are now moving in the back-end and wafer level packaging process. The results are mainly governed by the performance of the equipment i.e. the photo-tool. This is different for the permanent dielectric polymer material. The major difference in photo-resists and dielectric photo-polymer are the different functions of the material systems. Photo-resists are only temporary masks for subsequent process steps like etching and plating. This is different for the photo-polymers which are a permanent part of the future systems. In this paper a new technology is discussed which uses a laser scanning ablation process and BCB-Based Dry Film low k Permanent Polymer. Laser ablation of polymers is in principle not a new technology. Low speed and high cost was the major barrier. But the combination of a scanning technology together with quartz masks has opened this technology to overcome the limitation of the current photo-polymer process. The new technology is described in detail and the results of structuring BCB-Based Films down to less than 4 μm via diameter in a 15 μm thick film has been shown. The via side wall can be controlled by the fluence of the laser pulse. Test structures have been designed and fabricated to demonstrate the excellent electrical resistivity of the vias using a two-layer metallization process.

Thin film polymers, like PI, PBO and BCB are used in every wafer level packaging device. The improvement of the reliability of wafer-level packages and chip I/Os consider the choice of the polymer, which is used as dielectric on the chip, as a minor point. Because the production lines are normally fixed on one polymer and the high investments to evaluate the processing of an alternative polymer formulation in combination with costly reliability test seems to be not attractive till today. But the increased demands of advanced WLP and 3-D-Integration, which includes thin chips, chips stacking and higher routing densities, leads to reaching the limits of the common used material system combinations. The demand of better polymer films becomes evident by the fact that dozens of “next generation polymers” have entered the marked in the last years, which are tailored to get higher mechanical toughness and electrical performance aside of a nearly unchanged resolution capacity. The challenge for new polymer formulation is the evaluation of the processing and the generation of a reliable material property data base, which set the basics for any benchmarking to the already used polymer materials. The processing evaluation is done typically by the material supplier or the fab himself, where no special equipment is needed. The material property generation is a quite more complex topic because you need special equipment and partly the material need to be free standing without any substrate. This is also a handling issue, if we talk about thin films in the range of 5 to 20μm. This paper presents the reliable thin film polymer properties characterization of mechanical and electrical values. The measurements of the mechanical properties include the estimation of parameters like young's modulus, tensile strength, elongation at break, coefficient of thermal expansion, stress and time-temperature related effects. The evident topic of warpage related impacts by “new generation polymers” will be presented and discussed. Measurement structures on wafer-level are developed for the estimation of the electrical parameters, which allows a high accuracy and a device relevant value estimation. Parameters like break down voltage, leakage current, dielectric constant, loss factor are measured related to frequencies by MIM and resonator structures. We demonstrate with analyzing of the time-dependent dielectric breakdown (TDDB) of thin film polymers that there is an exponential linkage between field strength and the time till the breakthrough occurs. The mechanical and electrical properties were also investigated related to aging effects, when the application is running on elevated temperature. We examine a degradation of the mechanical and electrical performance, which should be taken into account for the mechanical system reliability and also for impedance controlled HF-application. This paper present advanced material characterization of thin film polymers which gives a guideline for the decision of the polymer related to the demands of the application.

The demands of higher routing density on wafer level are driven by multi-chip integrated fan-out packages and high I/O CSPs. New technologies and materials are necessary to generate lines and spaces down to 2 µm. Multi-metal layers are necessary for the higher wiring effort on panel level packaging (PLP) for example to contact dies which are embedded together. This places higher demands on the mechanical properties of the materials that are used for the redistribution layer. This paper presents a new excimer laser-enabled dual damascene process for ultra-fine routing for BEOL which was developed in a joint project with SUSS MicroTec. In the project, various materials e.g. low temperature cure polyimide, BCB and dry-film ABF materials were structured by using an excimer laser stepper with a reticle mask to pattern feature sizes below 4 µm with a high throughput. Micro-vias with a diameter below 5 µm were ablated with an aspect ratios up to 4 which is exceeding the photolithographic resolution limits of the established photosensitive thin-film polymers. The laser structuring allows the usage of innovative dielectric materials for WLPs/PLPs with optimized mechanical and electrical parameters, for example polymers with inorganic fillers like dry-film ABF material. Also, the ablations depth per laser pulse was investigated. The ablated lines and micro-vias were metallized by applying a galvanic process and CMP. The stepper-like system allows a sub-micron alignment accuracy with no need of a capture pad in the redistribution layers. Test multi-layer structures have been designed and fabricated with lines and spaces below 10 µm to demonstrate the dense routing capability with an excellent reliability which was verified by air-to-air thermal cycling (from -55 °C up to 125 °C).

The microelectronics industry is being continually challenged to decrease package size, lower power consumption and improve device performance for the mobile communication and server markets. In order to keep pace with these requirements, device manufacturers and assembly companies are focused on developing 3D-TSV integration schemes that will require stacking of 50 um thinned wafers with gaps of 15 microns or less. While conventional underfill approaches have been demonstrated for chip to chip and chip to wafer schemes, new materials and processes are required for wafer to wafer bonding given the target bondline and wafer handling issues. Photopatternable, low temperature curable dielectrics offer a potential solution to solve the issues by eliminating the need for flow and material entrapment during the joining process. This should result in a simplified bonding process that enables wafer to wafer bonding with improved device reliability. In this work, we will focus on validating the critical steps including patterning and bonding that are required to demonstrate the utility of this process using an aqueous developable benzocyclobutene based photodielectric material.

Polymeric coatings such as polyurethanes, acrylic, epoxies and silicones have been used for over 40 years to protect printed wiring boards (PWB) from moisture, handling and environmental influences. Special semiconductor grade polymers have been developed for chip passivation layers. Polyimide became the standard passivation layer for memory chips and other devices needing surface protection for handling and testing procedures. Photosensitive resins have been developed to reduce processing costs. Thin film polymers are used widely in the area of electronic packaging and as an interlayer dielectric (ILD) in nearly every electronic device. Typical layer thickness ranges from 5 μm up to 15 μm. These polymers films should be temperature stable up to range of 150°C (permanent), and for a short time up to 250°C and higher, depending on the soldering process of the components. This is the reason to use thermoset polymers in most cases. The coating process is the spin-coating technology. Spray coating and other techniques are only niche processes. The polymer supplied by the chemical company is a so-called pre-cursor consisting of a partially polymerized polymer in an organic solvent. Nearly all of the thin film polymers need a polymerization step, which is done in most cases by a thermal process after the deposition on the wafer. Polymerization changes the pre-polymer into a long-term stable and much more inherent polymerized dielectric layer. The polymerization process is generally called the cure or cure step of the process. But the definition “cure” does not mean in every case a fully finished polymerization reaction. Also partly cured polymer films are possible and becoming important if multiple layers have to be deposited. Partly polymerized layers have better adhesion to the following layer compared to fully cured ones. To get something more precise the following definitions have been used: partly cured or soft cured polymers for a 60 – 80 degree of polymerization, and full cured or hard cured for a complete polymerized layer.

3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered as a desirable 3D solution due to its cost effectiveness and matured technical background. For successful 3D stacking, precisely controlled bonding of the two substrates is necessary, so that various methods and materials have been developed over the last decade. Wafer bonding using polymeric adhesives has advantages. Surface roughness, which is critical in direct bonding and metal-to-metal bonding, is not a significant issue, as the organic adhesive can smooth out the unevenness during bonding process. Moreover, bonding of good quality can be obtained using relatively low bonding pressure and low bonding temperature. Benzocyclobutene (BCB) polymers have been commonly used as bonding adhesives due to their relatively low curing temperature (~250 °C), very low water uptake ( Two different BCB polymers, dry-etch type and photo type, are examined. Dry etch BCB is proper for full-area bonding, as it has low degree of cure and therefore less viscosity. Photo-BCB has advantages when a pattern (frame or via open) is to be structured on the film, since it is photoimageable (negative tone), and its moderate viscosity enables the film to sustain the patterns during the wafer bonding process. The effect of edge beads at the wafer rim area and the soft cure (before bonding) conditions on the bonding quality are also studied. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

A novel approach on wafer-level passivation of power devices using a thin, hermetic borosilicate glass layer as passivation or dielectric layer is presented here. The technology will be benchmarked to those conventional technologies. The glass layer is deposited at low temperatures (T < 100°C) using a plasma-enhanced e-beam deposition and can be structured by a lift-off process using a standard photo resist process for masking. The process flow is fully compatible with standard CMOS post processing and is integrated in a state-of-the-art production environment. The borosilicate thin-films yield breakdown voltages as high as 250 V/μm and a typical specific resistance of 1E17 Ohm/cm at room temperature, a value which is very close to the specific resistance of bulk borosilicate glass. The coefficient of thermal expansion of the borosilicate thin-film (∼3 ppm/K) is matched to silicon and enables systems to be reliable at high temperatures or in temperature cycling. Microstructured glass films were tested under extreme conditions e.g. up to temperatures as high as 650 °C as well as long-term temperature-humidity storage (85°C, 85% for 8000h). We demonstrate the use of borosilicate thin-films as inter-dielectric layers in wafer-level redistribution, replacing standard polymers such as BCB or PI as a drop-in solution. Process parameters and reliability results are discussed.

The ongoing efforts of increasing the resolution of image sensors for consumer products and the simultaneous demand for small camera systems led to a miniaturization in pixel sizes down to 1.4μm. This technological progress enables the fabrication of high pixel count imagers with comparably small dimensions (e.g. 9MPix with 4.88mm × 3.66mm / 3MPix with 2.86mm × 2.15mm). Further on, besides the impact of the pixel size on the lateral dimensions of the imager, manufacturing and packaging issues of the optical components and their integration with the imager influence the miniaturization. There are two effects which determine the lower limit of reasonable pixel miniaturization. Firstly, the increasing single-to-noise characteristics of the pixel leading to noisy images especially perturbing under low light conditions. Secondly, the diffraction limits which determines the smallest possible spot size when using a “perfect” lens without any spot blurring aberrations. As the latter depends from the f-number of the system, pixel miniaturization demands high speed lenses (low f-numbers) which additionally complicates the optical design and challenges their fabrication. The enabling key technology for wafer level packaging of camera systems based on top-side illuminated imagers are Through Silicon Vias (TSV) because they allow a redistribution on the backside of the wafer wherefore the active side remains unaffected and can be completely used for the optic assembly. Due to comparably relaxed pitches of the contact pads of mostly more than 100μm in most imaging applications, tapered vias with a polymer passivation are the straight forward approach and an economic reasonable TSV technology. Spray coating of polymers allows the use of low cure temperature materials also with severe topographies while spin coating can be a low cost alternative for applications where low silicon thicknesses of 40μm and below are allowed. Wafer bonding is the bridging technology which finally has to integrate the optics and the sensor part. Wafer stacks of up to a few millimeters have to be handled which can exhibit topographies on their backside while maintaining an accurate alignment of better than 5μm. The fabrication of camera packages using only wafer level technologies gets more complex and expensive the bigger the vertical dimension and/or the aspect ratio or shape of its comprising features becomes. The demands for a system integration on wafer level scales therefore with increasing pixel number and I/O — density. This paper outlines the prospects and limits of state of the art wafer-level-packaging technology for image sensor packaging with respect to the optical design. A process chain is presented for a micro camera device which was completely fabricated on wafer level having a die size of about 1mm × 1mm.

A novel process flow to manufacture miniaturized optical windows on wafer-level is presented. Those windows can be used for miniaturized optical products like high-brightness LEDs (HB-LED) and digital projection (DLP) as well as more complex optical data-communication, since integrated optical functions can be implemented with low tolerances. We explain the fabrication of cap-wafers having a shallow cavity with a depth of typically 10μm used in photo sensors and a unique manufacturing process for cap-wafers with a deep cavity of e.g. 300μm used in LED packaging. Those cap-wafers are used in wafer-level integration of advanced, miniaturized optical products. We discuss two options for wafer bonding i.e. bonding using adhesive as well as anodic bonding. As an example on product level a miniaturized photo sensor package, a pressure sensor package as well as a LED package is discussed.

The use of borosilicate glass for anodic wafer bonding to silicon is well established in industry. In this paper we present a matured approach, where a microstructured borosilicate glass thin-film instead of a bulk glass wafer is used as anodic bond layer. A glass layer with a thickness of 3 – 5 µm is sufficient for a stable bond at very moderate bond parameters with bond voltages in the range of 30 – 60 V at standard bond temperatures of around 300 °C and below. This enables the use of anodic bonding also for sensitive devices.

The novel wafer-level packaging (WLP) process invented allows hermetic capping of optical devices on wafer-level yielding miniaturized glass cavity windows on top of the optical area, at the same time leaving the contact area accessible for standard electrical connections i.e. wire bond. These optical cavity packages are used within standard chip-on-board (COB) assemblies for high performance optical applications providing high yields and utmost reliability for miniaturized optical devices at low costs.

A novel approach on wafer-level passivation using a thin, hermetic borosilicate glass layer replacing the polymers in redistribution is presented here. The technology will be benchmarked to those conventional technologies. The glass layer is deposited at low temperatures (T ≪ 100°C) using a plasma-enhanced e-beam deposition and can be structured by a lift-off process using a standard photo resist process for masking. The process flow is fully compatible with standard CMOS post processing and is integrated in a state-of-the-art production environment.

This special session on 3D TSV's will highlight some of the fabrication processes and used technologies to create vias from the frontside of an active circuit to its backside and potential implementation solutions to form complex systems leveraging these novel possibilities. General techniques for via formation are discussed as well as advanced integration solutions leveraging the power of 3D TSV's., Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/handle/2042/16838)

This paper describes the wafer level integration of coils, capacitors and resistors using copper/benzocyclobutene (Cu / BCB) thin film multi layer wiring. Examples for the application of this technology like integration of passives as above chip structures, realization of integrated passive devices as well as fabrication of thin film substrates with integrated passives prove Cu/BCB multi layer wiring to be a versatile base technology for the application-specific integration of passive components. The basic approach of using BCB as dielectric material is discussed to allow integrating high quality, but only small value capacitors in the range of some Pico Farads, which is due to the low dielectric constant of the material. In order to increase the capacitance density a new process allowing to replace the BCB locally by a thin glass layer in the areas of capacitors was evaluated. Since the BCB is only replaced in the areas of capacitors and still present in the other areas of the multi layer construction, the advantages of using BCB as dielectric material for multi layer wiring still apply. The evaluation of the new capacitor dielectric shows, that a 0.5 mum thick glass dielectric features a 26 times higher capacitance density compared to BCB with a thickness of 8 mum, as it has been used in the standard build-up for RF LC-filter integration so far. In order to show the capability of the new glass dielectric regarding size reduction, an existing layout of an integrated passive device with LC-filters is compared with a redesign based on the new technology. By using a 1 mum thick glass layer as dielectric instead of 8 mu thick BCB the total size of the device could be reduced by 28 %.

This paper analyzes two alternative under bump metallurgy (UBM) structures: sputtered TiW/Ni and electroless Ni/immersion Au (ENIG), with and without Pd. Wafers were fabricated with these UBM structures, solder applied with C4NP, and chip level stressing performed to determine the robustness of these alternative stack-ups. Microelectronic packaging continues the migration from wire bond to flip chip first level interconnect (FLI) to meet aggressive requirements for improved electrical performance, reduced size and weight. Analysis of these structures following multiple reflows and thermal cycling is presented.

For implantable neuroprosthetic devices, reliable packaging of the device is one of the requirements. Selection of proper packaging material and design is essential to protect the device from moist fluidic environment in the body as well as not to cause any harm to the implanted tissue. In particular, packaging needs to be designed carefully when the device operates wirelessly through inductive coupling between two coils, since the packaging could degrade the power transmission due to the losses in the packaging itself. In this study, the influence of the proposed packaging methods on the magnetic power transmission was investigated using numerical simulations with the help of finite element analysis. The simulation showed that both proposed packaging concepts of using a silicon lid and LTCC ferrite lid do not degrade the power transmission significantly at the selected frequency of 2.64 MHz.

The advent of micro and nanotechnologies along with integrated circuit technologies has led to many exciting solutions in medical field. One of the major applications of microsystems is microelectrodes interfacing neurons for large scale in vivo sensing, deep brain stimulation and recording. For biomedical microsystems, material selection is a challenge because biocompatibility has to be considered for implantable electronic devices. We are using flip chip bonding to integrate a signal processing IC to the Utah electrode array (UEA). Conventionally the flip chip process is used to bond a die to a substrate or interposer. In this work the electrical interconnects are made from the under bump metallization (UBM) on the UEA to the solder bumps on the IC. The UBM selection and reliability is one of the critical issues in the total reliability of a flip chip bumping and interconnection technology. The UBM was optimized to achieve improved interconnect strength, and its reliability was evaluated by conducting solder ball shear strength testing. The UBM reliability was tested with two solder metallurgies including AuSn and SnCu0.7. These solders are needed to allow two reflow processes to be used, an initial higher temperature (350 °C) and a second lower temperature process (250 °C).

A bumping technique which is based on electrochemical deposition (ECD) of various metals and metal alloys on wafer level will be presented and characterized in this paper. The machining of the single process steps principally origins from front-end technology widely using standard equipment, but mainly differing in structure sizes and layer thicknesses. Photosensitive polymers have been coated to repassivate the IC wafer and to serve as dielectric layers for I/O redistribution. Sputtering of the under-bump metallization (UBM), lithographical printing of resist pattern, electroplating of the bump metal, and selective etching of the plating base will be treated in detail. Different kinds of UBMs are used for the various bump metals. A sputtered Ti:W(N)/Au thin-film layer is used for the electroplating of Au and Au/Sn, and a Ti:W/Cu metallization acts as the seed layer for Cu and Ni/Au deposition as well as for the solder (SnPb37, PbSn5, SnAg3.5, SnCu0.7). Alternatively, other UBMs such as Ti/Ti:Ni/Ni, Ti/Au, and Cr/Cr:Cu/Cu has been qualified to generate several reliable solder bump metallurgies. Both spin-coating and spray-coating are used as a method to deposit the liquid photoresist onto the wafer. By applying a highly viscous system, layer thicknesses from 5 /spl mu/m up to 90 /spl mu/m with excellent thickness homogeneity and a precise pattern resolution for all standard wafer sizes can be achieved. A high standard of bump geometry as well as a high process quality and long term reliability can be obtained by carefully chosen electrolytes, well defined plating conditions, and specially developed microgalvanic equipment. Adequate wet etching solutions had to be formulated to get a neglectable corrosion affect on the bump surface and a minimum bump undercut. Thermal, mechanical, and electrical tests were performed to get statements about the reliability of the bumped devices.

Au/Sn solder bumps are mainly used for flip chip assembly of compound semiconductors in optoelectronic and RF applications. They allow a fluxless assembly which is required to avoid contamination of optical interfaces and the metallurgy is well suited to the final gold metallization on GaAs or InP. Flip chip assembly experiments were carried out using two layer Au/Sn bumps as plated without prior bump reflow. An RF and reliability test vehicles comprise a GaAs chip which was flip chip soldered on a silicon substrate. Temperature cycling tests with and without underfiller were performed. The different failure modes for underfilled and nonunderfilled samples were discussed and compared. Additional reliability tests were performed with flip chip bonding by gold thermocompression for comparison. The test results and the failure modes are discussed in detail.

A self-priming and photosensitive aqueous-base-developable benzocyclobutene (BCB)-based dielectric material curable in air is described. The polymer is made from divinylsiloxane benzocyclobutene and BCB-acrylic acid. Patterned films have high resolution, and via openings are scum-free without a descum operation. Whether cured in nitrogen or in air, the formulation produces a film with optical, electrical, thermal, and mechanical properties desired for many microelectronic applications, such as packaging applications and a planarization layer or insulation layer in display applications.