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This paper proposes a fully analytical loss model to reduce circling currents and improve the power efficiency of a class Φ2 inverter. Firstly, analytical expression of the switching node voltage is derived by analyzing its harmonic components. Based on the result, the power switch is modeled as a voltage source, where the circuit is simplified to a linear network and analytical expressions of branch currents are solved. Secondly, root mean square (RMS) values of branch currents and component losses are calculated to form the analytical loss model for a Φ2 inverter. The influence of circuit parameters on the circling current and power efficiency are thoroughly analyzed, which derives optimal design constraints to reduce circling currents of a class Φ2 inverter. Furthermore, detailed design guidance and equations are provided to calculate circuit parameters of a class Φ2 inverter, which reduces its circling currents and improves overall power efficiency. Finally, a class Φ2 inverter prototype is built, and experimental results demonstrate a 7% efficiency improvement compared to conventional empirical design methods. [ABSTRACT FROM AUTHOR]

This article proposes a unified pulsewidth-cycle (UPWC) control strategy to achieve mixed-mode operation and consistent valley switching (VS) for boost power factor correction converter. Compared with conventional single-mode controllers, it has a unified scheme to achieve single discontinuous conduction mode (DCM), single critical conduction mode (CRM), or mixed DCM/CRM operations in each half-line cycle. To regulate the input current as a sinusoid, the UPWC controller adopts a variable pulsewidth and a near-constant switching cycle under DCM, while adopts a constant pulsewidth and a variable switching cycle under CRM. To facilitate analysis, normalized mapping of operation modes is provided, along with the final pulsewidth and switching cycle. Furthermore, to ensure consistent VS, a controlled zero current detection method is proposed to fix the turn-on point of the power switch. No matter in DCM or CRM, consistent VS reduces both the switching loss and current distortion caused by parasitic resonance. To further reduce the current distortion caused by fixing the turn-on point, a compensation gain is provided that reshapes the input current as a sinusoid. Finally, through mixed DCM/CRM operation and consistent VS, the proposed UPWC controller achieves preferable performances in the power range, efficiency, power factor, and current distortion. [ABSTRACT FROM AUTHOR]

Digital peak current mode (DPCM) control is widely used for dc–dc converters operating in continuous current mode. However, current tracking delay (CTD) in the system is normally neglected in the modeling stage, which leads to poor compensator design and degraded performance. This paper investigates CTD effect in boost converter with different DPCM controls. Based on dynamic relationship between the reference current and actual inductor current, the CTD transfer functions are derived, which improves the accuracy of small signal model. Since CTD degrades the phase margin of the system, equivalent migration of right half plane zero is proposed to model CTD effect. This method is very simple and straightforward, which facilitates the compensator design. Furthermore, two novel DPCM control strategies with minimized CTD are proposed, and they are based on duty cycle restriction and duty cycle extension, respectively. Both controls greatly reduce the CTD effect and improve the response speed. Besides, the duty cycle extension benefits from an extended pulsewidth modulation (ExPWM). This optimizes the calculation algorithm and speed, while improving the time margin for digital calculations. Combined with the proposed models and controls, the CTD effect is greatly reduced. The effectiveness is verified through detailed simulations and experiments. [ABSTRACT FROM AUTHOR]

For boost power converter with Sensorless Current Mode (SCM) control, the inductor current is acquired by current estimator instead of current sensing. Without consideration of parasitics, the estimator is low-accurate, which affects system Small Signal Model (SSM) and degrades the control performance. In this paper, the issue is studied in frequency domain, and solved by a Corrective Frequency Compensation for Parasitics (CFCP) strategy. First, transfer functions for power converter, current estimator and current mode controller are given for frequency-domain analysis. Second, without consideration of parasitics, conventional proportional integral compensation is used to improve the system stability. Furthermore, with consideration of parasitics, converter main pole is replaced by two poles while a zero emerges at the origin. In order to cancel out the influence, the proposed CFCP strategy adopts a second-order transfer function to correct zero/pole variation induced by parasitics. Finally, steady state performance and transient response of the converter are improved, which are verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

Exploring high-performance controller for buck converter is challenging since it can be easily affected by converter model accuracy. In this paper, a novel nonaveraged current discrete-time (NCD) model is proposed, in which inductor current is expressed as time-varying equations during switch-on and switch-off states. It achieves higher accuracy than the conventional averaged model at high-frequency range, thus can be used to optimize high-speed controller design. Based on the NCD model, a multiloop minimum switching cycle (MMSC) control strategy, composed of output feedback (OF), line feed forward (LFF), and reference feed forward (RFF) loops, is proposed and tuned for buck converter operating in continuous conduction mode. Mutual influences among three loops are considered and eliminated by specifically designed LFF and RFF compensations, which adapt the OF compensation. With consideration of sampling and calculation delays, relationship between transient switching cycles and geometric center of controller poles is discovered from a calculated output voltage error series. Furthermore, theoretical minimum switching cycles are calculated by moving the center inside the unit cycle of complex plane, which ensures system stability. Moreover, load/line transient response and reference tracking time are simultaneously optimized to the minimum switching cycles. Effectiveness of the controller is proved by converter closed-loop pole/zero plots, transient response simulations, and experiments. [ABSTRACT FROM AUTHOR]

For discontinuous conduction mode (DCM) dc–dc converters with digital sensorless current mode (DSCM) control, an observed current error occurs, owing to a low-accuracy current observer. Moreover, a reference current error occurs due to a low-accuracy current controller or a finite dc gain of current loop. Conventionally, the observed current is compensated to increase current regulation accuracy, whereas the reference current error is neglected. However, for charge balance principle (CBP)-based DSCM (CBP-DSCM) control, this paper proves that the reference current should be compensated in a same quantity to that of observed current. Otherwise, single or unequal compensation leads to output voltage steady-state error. For this reason, a dual current error compensation strategy for CBP-DSCM control is proposed. It compensates the errors in a same quantity through a current error observer, which considers parasitics and calculates the current errors without approximation. To verify the proposed strategy, small-signal models with parasitics for both the converter and the controller are constructed by differential functions of key variables. Furthermore, converter stability is analyzed at typical operation condition, while the stability at various operation conditions is verified through robustness analysis. Finally, simulations and experimental results verify the analysis and the improved transient response of the converter. [ABSTRACT FROM AUTHOR]

For a sensorless predictive current controlled boost dc–dc converter, its small-signal model that contains a number of parasitic parameters, is derived in this paper. This model indicates that the type of system becomes type 0 even with the correction of voltage loop proportional–integral controller, leading to the existence of output voltage steady-state error. Then a self-correction differential current observer (SDCO) is proposed to eliminate this steady-state error and gain high transient response speed. The self-correction part of the SDCO makes the system become type 1 to achieve no steady-state error for output voltage, whereas the differential part can guarantee that the intermediate calculation results do not overflow. By carrying out a series of simulation verifications, further investigation proves that the proposed algorithm has good robustness. Finally, the effectiveness of the proposed algorithm is verified by experimental results. [ABSTRACT FROM PUBLISHER]

In this paper, a linearized discrete charge balance (LDCB) control strategy is proposed for buck converter operating in discontinuous conduction mode (DCM). For DC-DC power converters, discrete charge balance (DCB) control is an attractive approach to improve the output voltage transient response. However, as a non-linear control strategy, the algorithm is complex, which is difficult for implementation. To reduce the complexity, this paper proposes the LDCB control strategy that is derived through linearizing conventional DCB controller. By deriving the differential functions of the DCB control algorithm, the small signal relationship between the input and output of DCB controller is explored. Furthermore, based on the relationship, the LDCB controller is formed through three parallel feed loops to the duty ratio. As a linear control approach, the achieved LDCB controller is greatly simplified for implementation. This not only saves the hardware cost, but also reduces the calculation lag, which provides potential to improve the switching frequency. Besides, since the LDCB controller shares the same small signal model as that of DCB controller, it achieves similar control loop bandwidth and transient performance. Effectiveness of the proposed LDCB control is verified by zero/pole plots, transient analyses and experimental results. [ABSTRACT FROM AUTHOR]

This article reveals parasitics-induced current distortion (PCD) effect in discontinuous conduction mode boost power factor (PF) correction (PFC) converter. With consideration of parasitics, accurate inductor current is derived through total differential functions of line voltage, output voltage and duty cycle. Furthermore, the proposed current model is used to analyze PFC converter under conventional sensorless average current mode (SACM) control, which is achieved by a variable duty cycle. It is found that parasitics have considerable influence to the input current, and PCD leads to a degraded PF. In order to solve this issue, a current reshaping strategy is proposed to reduce the PCD phenomenon. Based on the damped current equations, a compensation gain is derived to reshape the input current, which reduces the current damping and distortion caused by parasitics. Both the PCD phenomenon and the current reshaping strategy are verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

This paper presents an Optimized Sensorless Charge Balance (OSCB) controller based on a damped current model for flyback converter operating in Discontinuous Conduction Mode (DCM). By solving total differential equations of non-ideal transformer currents, the damped current model is derived with consideration of parasitics, leakage inductance of transformer, and the Resistor-Capacitor-Diode (RCD) snubber circuit. Based on the proposed model, current observation and control algorithms of the Sensorless Charge Balance (SCB) controller are optimized, which forms the OSCB control strategy. The average current damping is considered in the equivalent discrete-time small signal model. Furthermore, frequency analyses show that OSCB controller achieves higher closed-loop bandwidth and lower overshoot than a SCB controller, which indicates an improved transient performance. Finally, both OSCB and conventional SCB controllers are experimentally evaluated on a flyback converter prototype. [ABSTRACT FROM AUTHOR]

For very high frequency (VHF) class Φ2 inverter, conventional design method requires complex tuning for parameters. Without fully quantitative calculations, the tuning highly depends on experience that cannot achieve optimal design. In this article, a target function design strategy is proposed based on quantitative harmonic weighting, which simplifies the design procedures and minimizes the switch voltage stress. First, the target switch voltage with minimized peak value is derived by optimizing the harmonic weighting. With the result, the power switch is modeled as a voltage source to simplify the calculations, where the branch currents are solved to provided fully quantitative analysis. Based on the analysis, optimal features of switching node impedance are derived to achieve the target switch voltage. In addition, basic constrains of the resonant tank are analyzed to reduce circling currents. Combining the optimal features and basic constrains of the resonant tank, the circuit parameters are calculated directly, which minimizes the switch voltage stress and improves power efficiency. Compared with conventional design, a 27.12 MHz prototype demonstrates 10.2% reduction in average switch voltage stress and 7.2% improvement in average efficiency. [ABSTRACT FROM AUTHOR]

This paper presents a triple-mode average current control (TACC) strategy to achieve unity power factor and reduce the current stress for a boost PFC converter. The controller switches among different modes in each half-line cycle, and smooth transition is ensured by mapping of the operation region. By adaptive mode shifting, it reduces the current stress and current distortion caused by non-linear effects. With valley current shaping and comparisons, the TACC controller accordingly incorporates three control laws to adapt different modes. In discontinuous conduction mode (DCM), a variable on-time is calculated while the modulation is equivalent to PWM. In critical conduction mode (CRM), a constant on-time is derived, while the switching cycle is modified to regulate the current average value. For both DCM and CRM, the switching cycle is slightly extended to realize valley switching. Furthermore, with valley current shaping, the proposed controller reuses the CRM calculation to form continuous conduction mode (CCM) control law. To make the control laws compatible, normalized mapping and design rules are provided with respect to mode boundaries. This allows the TACC controller to automatically switch among different modes. Finally, experimental results prove the effectiveness of the controller in reducing the current stress and enlarging the preferable power range. [ABSTRACT FROM AUTHOR]

For a sensorless predictive-peak-current-controlled boost converter, the output voltage steady-state error cannot be eliminated by voltage loop PI controller. The basic cause for this is investigated through analysis and theoretical approaches. To eliminate the voltage steady-state error and achieve high-accuracy current estimation, a comprehensive compensation strategy is proposed. First, a compensation algorithm for output voltage sampling is introduced. It can not only effectively eliminate the output voltage steady-state error but also guarantee current observer convergence. The compensation schemes for component parasitic parameter effects and switching delay are also investigated. With this comprehensive compensation strategy, both the system transient response and current estimation accuracy are greatly improved. Finally, the effectiveness of the proposed algorithm is verified by experimental results. [ABSTRACT FROM AUTHOR]

Abstract: This paper develops a novel dynamic framed slotted ALOHA (DFSA) algorithm based on Bayesian estimation to improve the throughput of the radio frequency identification (RFID) system. At first, four types of anti-collision algorithms for tag identification are analyzed. Then, the proposed DFSA based on Bayesian estimation is deduced and introduced. Compared with the conventional DFSA algorithms, this algorithm takes advantage of the evidence in previous frames as the a priori information of the current frame which can end up with more precise estimation of tag number and rational frame length adjustment. Finally, the common simulation tool from Matlab is used to demonstrate the effectiveness of the proposed new algorithm for the average throughput improvements of the RFID system. [Copyright &y& Elsevier]

This article investigates modeling and control approaches to optimize the efficiency and power factor for discontinuous conduction mode boost power factor correction converters. First, with detailed consideration of parasitics and GaN HEMT transients, the input and output charges of the converter are exactly derived, where the rate forms the comprehensive charge rate (CCR) model. Second, based on the CCR model, the overall efficiency is derived. Since the overall efficiency is only related to the input voltage, output voltage, and switching on-time, an optimal on-time is calculated to achieve the maximum efficiency. Furthermore, with the optimal on-time, a maximum efficiency average current (MEAC) controller is proposed to regulate the input current while maintaining the maximum efficiency. With the predefined optimal on-time, a switching cycle modulation method is adopted to regulate the input current as sinusoid, which improves the power factor to unity. Finally, effectiveness of the MEAC control strategy is verified by simulations and experiments. Compared with conventional constant on-time control, it achieves an optimized efficiency and power factor over a large operation range. [ABSTRACT FROM AUTHOR]

Integrators are widely used in industrial controls, signal processing, and computing. However, traditional resistor–capacitor integrators incur leakage errors and zero drift, hindering their accuracy. By contrast, spintronic devices with good scalability and endurance for memory and logic applications in digital circuits have yet to be studied for analog circuit elements. Here, we propose a single-device spintronic integrator based on the current-controlled magnetic domain wall (DW). Continuous DW motion and correlated changes in the anomalous Hall resistance (or magneto-resistance) are encoded as an analog output signal, which is modulated by an input current through the spin–orbit-torque effect. Waveform transformation and phase-shift functions are demonstrated using Hall-bar devices. The spintronic integrator could pave the way for the spin-based analog computing with high reliability, high endurance, and good compatibility with the CMOS process. [ABSTRACT FROM AUTHOR]

For switched mode power converters, boundary conduction mode (BCM) operation is an attractive alternative to improve the bandwidth, overall size, and efficiency. In this article, a sensorless ripple current mode (SRCM) controller is proposed to achieve inductor-deviation-tolerant BCM operation for boost converter. Compared to conventional approaches with current sensing or ZCD, the proposed controller relies on a digital algorithm to ensure consistent BCM operation. The algorithm calculates on/off durations of the main switch so that the inductor current valley value converges to zero. The convergence process is proved by a damped current model with considerations of parasitics and output voltage ripple. Since the convergence is not related to the inductor value, the SRCM controller achieves inductor-deviation-tolerant BCM operation. Furthermore, to improve the power efficiency, an optimal transition condition and a compensation time are adopted to achieve valley switching (VS). Finally, both consistent BCM operation and VS are achieved by the proposed control strategy. Simulations and experimental results prove that the controller effectively improves the closed-loop stability, the robustness to inductor deviation, and the power efficiency. [ABSTRACT FROM AUTHOR]

Switched mode power converters are nonlinear systems, and it is a constant challenge to improve their modeling accuracy and control performance. In this paper, a State Switched Discrete-time Model (SSDM) is proposed, which achieves a higher accuracy at a high frequency than that of conventional state averaged models. Instead of averaging the converter states for approximation, the states within each switching cycle are considered in the modeling. Based on total differential equations of switching-ON and switching-OFF durations, the inductor current and output voltage within a cycle are accurately calculated, which derives the SSDM. Furthermore, a Digital Predictive Voltage Programmed (DPVP) control strategy is derived through the SSDM. Through voltage prediction, a suitable duty ratio is calculated that regulates the output voltage to its reference value in the minimum switching cycles. In this way, the converter achieves a very fast load/line transient response and reference tracking speed, and it exhibits a high stability under deviated inductance. Finally, the accuracy of SSDM and the system stability are proved by frequency response analyses and experiments. [ABSTRACT FROM AUTHOR]

Static Random Access Memory (SRAM) Physical Unclonable Functions (PUFs) are some of the most popular PUFs that provide a highly-secured solution for secret key storage. Given that PUF responses are noisy, the key reconstruction must use error correcting code (ECC) to reduce the noise. Repetition code is widely used in resource constrained systems as it is concise and lightweight, however, research has shown that repetition codes can lead to information leakage. In this paper we found that the strongest cell distribution in a SRAM array may leak information of the responses of SRAM PUF when the repetition code is directly applied. Experimentally, on an ASIC platform with the HHGRACE 0.13 μm process, we recovered 8.3% of the measured response using the strongest cells revealed by the helper data, and we finally obtained a clone response 79% similar to weak response using the public helper data. We therefore propose Error Resistant Fuzzy Extractor (ERFE), a 4-bit error tolerant fuzzy extractor, that extracts the value of the sum of the responses as a unique key and reduces the failure rate to 1.8 × 10−8 with 256 bit entropy. [ABSTRACT FROM AUTHOR]