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Although decoupled plasma nitridation (DPN) post high-k dielectric deposition shows the better threshold voltage shift than post deposition anneal (PDA), the non-adequate plasma nitrogen (N) concentration and anneal temperature still can dominate the device performance. Using these two variables to probe the impact of HK deposition integrity and the interface quality between channel and gate dielectric is an undetected and published topic. In the experiment, the lower N-concentration and higher anneal temperature is beneficial to the higher drive current and lower threshold for NMOSFET. However, the PMOSFET prefers the lower anneal temperature as well as lower N-concentration. Additionally, the phenomena for the combination of DPN process and strain engineering causing the non-uniform trend distribution of subthreshold swing with device channel lengths were exposed.

Reported literatures have investigated the effects of pMOSFETs with embedded SiGe source/drain stressor, but devices incorporated with biaxial strain and embedded SiGe source/drain has not been clearly probed. In this study, the characteristics of devices containing biaxial strain and embedded SiGe source/drain stressor as well as different channel lengths were explored. According to the experimental results at high temperature stress, the saturation current of the embedded SiGe source/drain pMOSFETs degraded 5.5%, which was more serious than Si-control devices' 4.8% degradation. It is presumable that embedded SiGe source/drain induces more traps or interface states on the channel surface. In the channel hot carrier stress, the worst case in current degradation also demonstrated the identical trend.

The embedded SiGe source/drain stressor helpful to promote the drive current involves etching out the source/drain silicon and replacing it with SiGe filler. This process uses the lattice mismatch between silicon and germanium atoms making the silicon channel compressive. This compressive stress enhances hole mobility, and the pMOSFET performance can be enhanced. In this study, the characteristics of devices contained biaxial strain in channel and embedded SiGe source/drain stressor with different channel lengths and the channel hot carrier (CHC) in short channel pMOSFETs was explored, too.

Strained engineering in nano process technology is considered to be a promising enhancements on the electric characteristics of MOSFET devices. Both tensile and compressive strains are applied to NMOS and PMOS individually using silicon nitride as contact etching stop layer (CESL). As appeared in this study, the electrical characteristics are to be compared with or without strain on 10µm/10µm (channel length/ width) at various temperatures, and more benefits of compressive CESL and tensile CESL for NMOS and PMOS, respectively, are seen. One thus goes on to check with the trans-conductance (g m ) and the leakage current. The data that were shown assure us the next-generation promising devices.

The embedded SiGe source/drain (S/D) stressor applies the lattice mismatch between silicon and germanium atoms making silicon channel generate compressive strain in the surface channel. The compressive strain enhances hole mobility due to raising the weighting factor of the light hole contribution, causing the improvement of the pMOSFETs performance. Previous reports have investigated the effects of pMOSFETs with embedded SiGe S/D stressor. But, devices incorporated with biaxial strain and embedded SiGe S/D have not been clearly investigated. In this work, not only were the characteristics of devices containing biaxial strain and embedded SiGe S/D stressor with different channel lengths exposed, but the channel-hot-carrier (CHC) effect in short-channel pMOSFETs was also followed with interest. The experimental results show that the biaxial strain achieved higher carrier mobility in long channel. However, this strain reduces its mobility enhancement effect when the channel length becomes shorter. In additi...

In the nano-regime MOSFET devices, the punch-through effect is more distinct, retarding the reliability tolerance, such as electro-static discharge or latch-up applications. Through the measurement in various device lengths under contact-etch-stop-layer strain process or without strain effect for 45 nm complementary MOS process, the difference of punch-through effect and junction breakdown integrity were able to be classified and exhibited in design applications. After tested data analysis, the junction breakdown issue in PMOSFET was usually greater than that in NMOSFET due to the doping concentrations and the doping species. Generally, the junction breakdown value is independent of channel length variation except the existence of some damage close to the gate/source or gate/drain fringe. In addition, the punch-through voltage for PMOSFET as source/drain current IDS = 1 μA is also larger than that observed for NMOSFET.